Datasheet

dsPIC30F4011/4012

TABLE 14-1: QEI REGISTER MAP

(1)

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

QEICON 0122 CNTERR

— QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB — TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 0000 0000

DFLTCON 0124

— — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 0000 0000 0000

POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000

MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111

ADPCFG 02A8

— — — — — — — PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

Legend: — = unimplemented bit, read as ‘0’

Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.