Datasheet

© 2010 Microchip Technology Inc. DS70135G-page 231
dsPIC30F4011/4012
M
Microchip Internet Web Site.............................................. 235
Modulo Addressing ............................................................. 38
Applicability................................................................. 40
Operation Example ..................................................... 39
Start and End Address................................................ 39
W Address Register Selection .................................... 39
Motor Control PWM Module................................................ 95
Register Map............................................................. 105
MPLAB ASM30 Assembler, Linker, Librarian ................... 172
MPLAB Integrated Development Environment Software .. 171
MPLAB PM3 Device Programmer .................................... 174
MPLAB REAL ICE In-Circuit Emulator System................. 173
MPLINK Object Linker/MPLIB Object Librarian ................ 172
O
Operating MIPS vs. Voltage.............................................. 176
Oscillator
Configurations........................................................... 152
Fail-Safe Clock Monitor .................................... 154
Fast RC (FRC).................................................. 153
Initial Clock Source Selection ........................... 152
Low-Power RC (LPRC)..................................... 153
LP ..................................................................... 153
Phase Locked Loop (PLL) ................................ 153
Start-up Timer (OST) ........................................ 152
Operating Modes (Table).......................................... 150
Oscillator Selection ........................................................... 149
Output Compare Module..................................................... 83
During CPU Idle Mode................................................ 86
During CPU Sleep Mode............................................. 86
Interrupts..................................................................... 86
Register Map............................................................... 87
P
Packaging ......................................................................... 219
Details....................................................................... 221
Marking ..................................................................... 219
Pinout Descriptions
dsPIC30F4011............................................................ 12
dsPIC30F4012............................................................ 14
POR. See Power-on Reset.
Position Measurement Mode .............................................. 91
Power-Saving Modes........................................................ 159
Idle ............................................................................ 160
Sleep......................................................................... 159
Power-Saving Modes (Sleep and Idle) ............................. 149
Program Address Space..................................................... 25
Construction................................................................ 26
Data Access From Program Memory Using Table In-
structions ............................................................ 27
Data Access From, Address Generation .................... 26
Memory Map............................................................... 25
Table Instructions
TBLRDH ............................................................. 27
TBLRDL .............................................................. 27
TBLWTH ............................................................. 27
TBLWTL.............................................................. 27
Program Counter ................................................................ 18
Program Data Table Access (lsw) ...................................... 27
Program Data Table Access (MSB).................................... 28
Program Space Visibility
Window into Program Space Operation...................... 29
Programmable Digital Noise Filters .................................... 91
Programmer’s Model........................................................... 18
Diagram...................................................................... 19
Programming Operations.................................................... 51
Algorithm for Program Flash....................................... 51
Erasing a Row of Program Memory ........................... 51
Initiating the Programming Sequence ........................ 52
Loading Write Latches................................................ 52
Protection Against Accidental Writes to OSCCON........... 154
PWM Duty Cycle Comparison Units................................. 100
Duty Cycle Register Buffers ..................................... 100
PWM Fault Pin.................................................................. 103
Enable Bits ............................................................... 103
Fault States .............................................................. 103
Input Modes.............................................................. 103
Cycle-by-Cycle ................................................. 103
Latched............................................................. 103
PWM Operation During CPU Idle Mode ........................... 104
PWM Operation During CPU Sleep Mode........................ 104
PWM Output and Polarity Control..................................... 103
Output Pin Control.................................................... 103
PWM Output Override ...................................................... 102
Complementary Output Mode .................................. 102
Synchronization........................................................ 102
PWM Period........................................................................ 98
PWM Special Event Trigger.............................................. 104
Postscaler................................................................. 104
PWM Time Base................................................................. 97
Continuous Up/Down Count Modes ........................... 97
Double Update Mode.................................................. 98
Free-Running Mode.................................................... 97
Postscaler................................................................... 98
Prescaler .................................................................... 98
Single-Shot Mode....................................................... 97
PWM Update Lockout....................................................... 104
Q
QEI Module
Operation During CPU Sleep Mode ........................... 91
Timer Operation During CPU Sleep Mode ................. 91
Quadrature Encoder Interface (QEI)................................... 89
Interrupts .................................................................... 92
Logic........................................................................... 90
Operation During CPU Idle Mode............................... 92
Register Map .............................................................. 93
Timer Operation During CPU Idle Mode..................... 92
R
Reader Response............................................................. 236
Reset ........................................................................ 149, 155
BOR, Programmable ................................................ 157
Oscillator Start-up Timer (OST)................................ 149
POR.......................................................................... 155
Long Crystal Start-up Time............................... 157
Operating Without FSCM and PWRT............... 157
Power-on Reset (POR)............................................. 149
Power-up Timer (PWRT).......................................... 149
Programmable Brown-out Reset (BOR) ................... 149
Reset Sequence ................................................................. 45
Reset Sources............................................................ 45
Revision History................................................................ 227
RTSP
Control Registers........................................................ 50
NVMADR............................................................ 50
NVMADRU ......................................................... 50
NVMCON............................................................ 50
NVMKEY ............................................................ 50
Operation.................................................................... 50