Datasheet

dsPIC30F4011/4012
DS70135G-page 122 © 2010 Microchip Technology Inc.
FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM
Read
URX8
UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
– Generate Flags
– Generate Interrupt
UxRXIF
UxRX
· Start bit Detect
Receive Shift Register
Control
Signals
UxSTA
– Shift Data Characters
Read Read
Write
Write
to Buffer
8-9
(UxRSR)
PERR
FERR
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
16x Baud Clock from
Baud Rate Generator
÷ 16 Divider