Datasheet

© 2010 Microchip Technology Inc. DS70135G-page 113
dsPIC30F4011/4012
17.0 I
2
C™ MODULE
The Inter-Integrated Circuit (I
2
C™) module provides
complete hardware support for both Slave and Multi-
Master modes of the I
2
C serial communication
standard with a 16-bit interface.
This module offers the following key features:
•I
2
C Interface supporting both Master and Slave
Operation
•I
2
C Slave mode supports 7-bit and 10-bit address-
ing
•I
2
C Master mode supports 7-bit and 10-bit
addressing
•I
2
C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I
2
C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
•I
2
C supports Multi-Master Operation; detects bus
collision and will arbitrate accordingly
17.1 Operating Function Description
The hardware fully implements all the master and slave
functions of the I
2
C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Thus, the I
2
C module can operate either as a slave or
a master on an I
2
C bus.
17.1.1 VARIOUS I
2
C MODES
The following types of I
2
C operation are supported:
•I
2
C slave operation with 7-bit addressing
•I
2
C slave operation with 10-bit addressing
•I
2
C master operation with 7-bit or 10-bit addressing
See the I
2
C programmer’s model in Figure 17-1.
17.1.2 PIN CONFIGURATION IN I
2
C MODE
I
2
C has a 2-pin interface. The SCL pin is clock and the
SDA pin is data.
17.1.3 I
2
C REGISTERS
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read-only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 17-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 17-2.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
FIGURE 17-1: PROGRAMMER’S MODEL
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Note: Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
bit 7
bit 0
I2CRCV (8 bits)
bit 7
bit 0
I2CTRN (8 bits)
bit 8
bit 0
I2CBRG (9 bits)
bit 15
bit 0
I2CCON (16-bits)
bit 15
bit 0
I2CSTAT (16-bits)
bit 9
bit 0
I2CADD (10-bits)