dsPIC30F4011/4012 Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC30F4011/4012 High-Performance, 16-Bit Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 Special Digital Signal Controller Features: CMOS Technology: • • • • • Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical) • Data EEPROM memory: - 100,000 erase/write cycle (min.
dsPIC30F4011/4012 Pin Diagrams 40-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dsPIC30F4011 MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 VDD VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 OC4/RD3 VSS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2
dsPIC30F4011/4012 Pin Diagrams (Continued) 1 2 3 4 5 6 7 8 9 10 11 dsPIC30F4011 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RC15 OSC1/CLKI VSS VSS VDD VDD AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 PWM2L/RE2 NC PWM1H/RE1 PWM1L/RE0 AVSS AVDD MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 12 13 14 15 16 17 18 19 20 21 22 PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 VSS VDD VDD PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 39 3
dsPIC30F4011/4012 Pin Diagrams (Continued) 28-Pin SPDIP and SOIC dsPIC30F4012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 VDD EMUD2/OC2/IC2/INT2/RD1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF
dsPIC30F4011/4012 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 17 3.0 Memory Organization ..........................................................................
dsPIC30F4011/4012 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 1-1: dsPIC30F4011 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 16 Data Latch Y Data RAM (1 Kbyte) Address Latch 16 24 Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch X Data RAM (1 Kbyte) Address Latch 16 16 X RAGU X WAGU 16 24 16 EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/R
dsPIC30F4011/4012 FIGURE 1-2: dsPIC30F4012 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 Data Latch Y Data RAM (1 Kbyte) Address Latch 16 24 Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 16 16 X RAGU X WAGU 16 24 16 Data Latch X Data RAM (1 Kbyte) Address Latch EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/R
dsPIC30F4011/4012 Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F4011 I/O PIN DESCRIPTIONS Pin Type Buffer Type AN0-AN8 I Analog Analog input channels.
dsPIC30F4011/4012 TABLE 1-1: Pin Name dsPIC30F4011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Type Buffer Type Description OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. OSC2 I/O PGD PGC I/O I ST ST In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin.
dsPIC30F4011/4012 Table 1-2 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-2: dsPIC30F4012 I/O PIN DESCRIPTIONS Pin Type Buffer Type AN0-AN5 I Analog Analog input channels.
dsPIC30F4011/4012 TABLE 1-2: Pin Name dsPIC30F4012 I/O PIN DESCRIPTIONS (CONTINUED) Pin Type Buffer Type Description OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. OSC2 I/O PGD PGC I/O I ST ST In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin.
dsPIC30F4011/4012 NOTES: DS70135G-page 16 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 2.0 Note: 2.1 CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 2.2 Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped.
dsPIC30F4011/4012 FIGURE 2-1: dsPIC30F4011/4012 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC30F4011/4012 2.3 Divide Support The dsPIC DSCs feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. 2. 3. 4. 5. DIVF – 16/16 signed fractional divide DIV.sd – 32/16 signed divide DIV.ud – 32/16 unsigned divide DIV.s – 16/16 signed divide DIV.
dsPIC30F4011/4012 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 2.4.1 MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/ scaler is a 33-bit value, which is sign-extended to 40 bits.
dsPIC30F4011/4012 The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and is saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
dsPIC30F4011/4012 2.4.2.4 Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.
dsPIC30F4011/4012 Note: 3.1 MEMORY ORGANIZATION FIGURE 3-1: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> Instruction Access User TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA<15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA<15:0> Program Space Visibility User FIGURE 3-2: <0> PC<22:1> 0 0 PSVPAG<7:0> 0 Data EA<14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Us
dsPIC30F4011/4012 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed; via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.
dsPIC30F4011/4012 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
dsPIC30F4011/4012 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x000100 0x0000 EA<15> = 0 Data Space EA PSVPAG(1) 0x00 8 15 16 0x8000 15 EA<15> = 1 15 Address Concatenation 23 23 15 0 0x001200 Upper Half of Data Space is Mapped into Program Space 0x007FFE 0xFFFF BSET MOV MOV MOV CORCON,#2 #0x00, W0 W0, PSVPAG 0x9200, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-b
dsPIC30F4011/4012 FIGURE 3-6: dsPIC30F4011/4012 DATA SPACE MEMORY MAP MSB Address MSB 2-Kbyte SFR Space 0x0001 LSB Address 16 bits LSB 0x0000 SFR Space 0x07FE 0x0800 0x07FF 0x0801 X Data RAM (X) 2-Kbyte SRAM Space 0x0BFF 0x0C01 0x0BFE 0x0C00 4096 Bytes Near Data Space Y Data RAM (Y) 0x0FFF 0x0FFE 0x1001 0x1000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70135G-page 30 0xFFFE © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-7: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 3.2.2 DATA SPACES 3.2.3 The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.
dsPIC30F4011/4012 All byte loads into any W register are loaded into the LSB; the MSB is not modified. A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.
SFR Name CORE REGISTER MAP(1) Address (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State W0 0000 W0/WREG 0000 0000 0000 0000 W1 0002 W1 0000 0000 0000 0000 W2 0004 W2 0000 0000 0000 0000 W3 0006 W3 0000 0000 0000 0000 W4 0008 W4 0000 0000 0000 0000 W5 000A W5 0000 0000 0000 0000 W6 000C W6 0000 0000 0000 0000 W7 000E W7 0000 0000 0000 0000 W8 0010 W8 0000 0000 0000 0000 W9 0012 W9
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012 NOTES: DS70135G-page 36 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 4.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
dsPIC30F4011/4012 4.2.1 START AND END ADDRESS 4.2.2 The Modulo Addressing scheme requires that a start and end address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses.
dsPIC30F4011/4012 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
dsPIC30F4011/4012 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1
dsPIC30F4011/4012 NOTES: DS70135G-page 42 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 5.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 5.1 Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assignable priority levels start at 0 as the lowest priority, and level 7 as the highest priority.
dsPIC30F4011/4012 5.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset, which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location, immediately followed by the address target for the GOTO instruction.
dsPIC30F4011/4012 5.3.1.2 Address Error Trap This trap is initiated when any of the following circumstances occurs: 1. 2. 3. 4. A misaligned data word access is attempted. A data fetch from an unimplemented data memory location is attempted. A data access of an unimplemented program memory location is attempted. An instruction fetch from vector space is attempted. Note: 5. 6.
dsPIC30F4011/4012 5.4 Interrupt Sequence 5.5 All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending interrupt request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the interrupt enable (IECx) register is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated.
SFR Name ADR INTERRUPT CONTROLLER REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State — 0000 0000 0000 0000 INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF IFS1 0086 — — — — C1IF — U2TX
dsPIC30F4011/4012 6.0 FLASH PROGRAM MEMORY Note: 6.2 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time. Each panel of program memory contains write latches that hold 32 instructions of programming data.
dsPIC30F4011/4012 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
dsPIC30F4011/4012 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer.
© 2010 Microchip Technology Inc. NVM REGISTER MAP(1) TABLE 6-1: File Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 54 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 7.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-2.
dsPIC30F4011/4012 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM; erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADRU/NVMADR. c) Enable NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
dsPIC30F4011/4012 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block.
dsPIC30F4011/4012 7.4 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in.
dsPIC30F4011/4012 NOTES: DS70135G-page 60 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 8.0 Note: I/O PORTS the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046).
dsPIC30F4011/4012 FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Output Multiplexers Peripheral Module Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Peripheral Output Data 0 1 PIO Module Output Enable Output Data 0 Read TRIS I/O Pad Data Bus D WR TRIS CK Q TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT 8.
© 2010 Microchip Technology Inc. TABLE 8-1: SFR Name dsPIC30F4011 PORT REGISTER MAP(1) Addr.
SFR Name dsPIC30F4012 PORT REGISTER MAP(1) Addr.
dsPIC30F4011/4012 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change of state on selected input pins. This module is capable of detecting input change of states, even in Sleep mode, when the clocks are disabled. There are 10 external signals (CN0 through CN7, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a change of state.
dsPIC30F4011/4012 NOTES: DS70135G-page 66 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 9.0 Note: TIMER1 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) PR1 Equal Comparator x 16 TSYNC 1 Sync TMR1 Reset 0 0 1 Q D Q CK TGATE TCS TGATE 2 1x LPOSCEN SOSCI Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON<6>), must be set to enable this mode.
dsPIC30F4011/4012 9.4 Timer Interrupt 9.5.1 The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the Period register, the T1IF bit is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The Timer Interrupt Flag, T1IF, is located in the IFS0 control register in the interrupt controller.
SFR Name Addr. TMR1 0100 PR1 0102 T1CON 0104 Legend: Note 1: TIMER1 REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer1 Register Period Register 1 TON — TSIDL — — — — — — TGATE u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 0 T3IF Event Flag 1 Q D Q CK TGATE(T2CON<6>) TCS TGATE TGATE (T2CON<6>) PR2 TON T2CK Note: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation.
dsPIC30F4011/4012 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Reset TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE T2IF Event Flag Comparator x 16 TGATE TON T2CK TCKPS<1:0> 2 1x FIGURE 10-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Reset TMR3 0 1 Q D Q CK TGATE TCS TGATE T3IF Event Flag Comparator x 16 TGATE Sync TON 1x 01 TCY Note: TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 The dsPIC30F4011/4012 devices do no
dsPIC30F4011/4012 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
© 2010 Microchip Technology Inc. TABLE 10-1: SFR Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 76 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 11.0 Note: TIMER4/5 MODULE The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046).
dsPIC30F4011/4012 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Comparator x 16 Reset TMR4 Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE T4IF Event Flag TCKPS<1:0> TON T4CK(1) 2 1x Note 1: FIGURE 11-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 T4CK is not implemented and this line is tied to VSS.
© 2010 Microchip Technology Inc. TABLE 11-1: SFR Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 80 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 12.0 INPUT CAPTURE MODULE Note: The key operational features of the input capture module are: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046).
dsPIC30F4011/4012 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • • • • • Capture every falling edge Capture every rising edge Capture every 4th rising edge Capture every 16th rising edge Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM<2:0> (ICxCON<2:0>). 12.1.1 12.1.
dsPIC30F4011/4012 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events. The selection number is set by control bits, ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respective Capture Channel Interrupt Enable (ICxIE) bit.
SFR Name Addr.
dsPIC30F4011/4012 13.0 Note: OUTPUT COMPARE MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.
dsPIC30F4011/4012 13.4.2 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1. EQUATION 13-1: PWM PERIOD PWM period = [(PRx) + 1] • 4 • TOSC • (TMRX prescale value) PWM frequency is defined as 1/[PWM period].
dsPIC30F4011/4012 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state. For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin will remain low.
© 2010 Microchip Technology Inc. TABLE 13-1: SFR Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 90 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 14.
dsPIC30F4011/4012 14.1 Quadrature Encoder Interface Logic A typical, incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward.
dsPIC30F4011/4012 14.3 Position Measurement Mode There are two Measurement modes which are supported and are termed x2 and x4. These modes are selected by the QEIM<2:0> (QEICON<10:8>) mode select bits. When control bits, QEIM<2:0> = 100 or 101, the x2 Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter increment rate. Every rising and falling edge of the Phase A signal causes the position counter to be incremented or decremented.
dsPIC30F4011/4012 14.7 QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface, or as a 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI module will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR.
© 2010 Microchip Technology Inc. TABLE 14-1: SFR Name QEICON Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 96 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 15.0 Note: MOTOR CONTROL PWM MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs FLTACON Fault Pin Control SFRs OVDCON PWM Manual Control SFR PWM Generator 3 16-bit Data Bus PDC3 Buffer PDC3 Comparator PWM Generator 2 PTMR PWM3H Channel 3 Dead-Time Generator and Override Logic Channel 2 Dead-Time Generator and Override Logic Comparator PWM3L PWM2H Output Driver PWM2L Block PWM Generator 1 Channel 1 Dead-Time Generator and Override Logic P
dsPIC30F4011/4012 15.1 PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a read-only status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR.
dsPIC30F4011/4012 15.1.4 DOUBLE UPDATE MODE 15.2 PWM Period In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. PTPER is a 15-bit register and is used to set the counting period for the PWM time base. PTPER is a double-buffered register.
dsPIC30F4011/4012 15.3 Edge-Aligned PWM Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free-Running or Single-Shot mode. For edge-aligned PWM outputs, the output has a period specified by the value in PTPER and a duty cycle specified by the appropriate duty cycle register (see Figure 15-2). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the duty cycle register matches PTMR.
dsPIC30F4011/4012 15.5 PWM Duty Cycle Comparison Units There are three 16-bit Special Function Registers (PDC1, PDC2 and PDC3) used to specify duty cycle values for the PWM module. The value in each duty cycle register determines the amount of time that the PWM output is in the active state. The duty cycle registers are 16-bits wide. The LSb of a duty cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. 15.5.
dsPIC30F4011/4012 15.7.1 DEAD-TIME GENERATORS Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure 15-4, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. 15.7.2 DEAD-TIME RANGES The amount of dead time provided by the dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value.
dsPIC30F4011/4012 15.8 Independent PWM Output An Independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PTMODx bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent Output mode and both I/O pins are allowed to be active simultaneously.
dsPIC30F4011/4012 15.11 PWM Output and Polarity Control 15.12.2 There are three device Configuration bits associated with the PWM module that provide PWM output pin control: The FLTACON Special Function Register has six bits that determine the state of each PWM I/O pin when it is overridden by a Fault input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state.
dsPIC30F4011/4012 15.13 PWM Update Lockout 15.14.1 For a complex PWM application, the user may need to write up to three duty cycle registers and the Time Base Period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio.
© 2010 Microchip Technology Inc. TABLE 15-1: SFR Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 108 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 16.0 Note: SPI™ MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 16.2 Framed SPI Support the SS1 pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. The module supports a basic framed SPI protocol in Master or Slave mode.
dsPIC30F4011/4012 16.3 Slave Select Synchronization The SS1 pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode, with SS1 pin control enabled (SSEN = 1). When the SS1 pin is low, transmission and reception are enabled and the SDO1 pin is driven. When SS1 pin goes high, the SDO1 pin is no longer driven. Also, the SPI module is resynchronized and all counters/control circuitry are reset.
SPI1 REGISTER MAP(1) SFR Name Addr. Bit 15 SPI1STAT 0220 SPI1CON 0222 SPI1BUF 0224 Legend: Note 1: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012 17.0 Note: I2C™ MODULE 17.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 17-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70135G-page 114 Write I2CBRG FCY Read © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 17.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 LSbs of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
dsPIC30F4011/4012 17.4.1 10-BIT MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 17.
dsPIC30F4011/4012 17.7 Interrupts The I2C module generates two interrupt flags, MI2CIF (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 17.8 Slope Control 2 The I C standard requires slope control on the SDA and SCL signals for Fast mode (400 kHz).
dsPIC30F4011/4012 17.12.2 I2C MASTER RECEPTION Master mode reception is enabled by programming the receive enable (RCEN) bit (I2CCON<3>). The I2C module must be Idle before the RCEN bit is set, otherwise the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin toggles and data is shifted in to the I2CRSR on the rising edge of each clock.
© 2010 Microchip Technology Inc. TABLE 17-2: SFR Name Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 120 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 18.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046).
dsPIC30F4011/4012 FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE URX8 Write UxSTA UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 1 UxRX Control Signals FERR Load RSR to Buffer Receive Shift Register (UxRSR) From UxTX PERR 8-9 LPBACK 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic ÷ 16 Divider 16x Baud Clock from Baud Rate Generator UxRXIF DS7013
dsPIC30F4011/4012 18.2 18.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input, respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 18.2.2 18.3 18.3.1 Disabling the UART module resets the buffers to empty states.
dsPIC30F4011/4012 18.3.4 TRANSMIT INTERRUPT The Transmit Interrupt Flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word.
dsPIC30F4011/4012 18.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read-only FERR bit is buffered along with the received data; it is cleared on any Reset. 18.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
dsPIC30F4011/4012 18.9 Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 18.10.
© 2010 Microchip Technology Inc. TABLE 18-1: UART1 REGISTER MAP(1) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 — ALTIO Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 WAKE LPBACK ABAUD U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — U1TXREG 0210 — — — — — U1RXREG 0212 — — — — — U1BRG 0214 Legend: Note 1: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012 NOTES: DS70135G-page 128 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 19.0 Note: 19.1 CAN MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1(1) BUFFERS Acceptance Filter RXF2(1) TXERR MESSAGE TXLARB TXREQ TXABT TXERR TXB2(1) MESSAGE TXLARB TXREQ TXABT TXB1(1) MESSAGE TXERR TXLARB TXREQ TXABT TXB0(1) A c c e p t RXB0(1) Message Queue Control Transmit Byte Sequencer Acceptance Mask RXM0(1) Acceptance Filter RXF3(1) Acceptance Filter RXF0(1) Acceptance Filter RXF4(1) Acceptance Filter RXF1(1) Acceptance Filter RXF5(1) Iden
dsPIC30F4011/4012 19.3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Loopback Mode Error Recognition Mode Modes are requested by setting the REQOP<2:0> bits (C1CTRL<10:8>). Entry into a mode is acknowledged by monitoring the OPMODE<2:0> bits (C1CTRL<7:5>).
dsPIC30F4011/4012 19.4 19.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the message assembly buffer (MAB). There are two receive buffers, visibly denoted as RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
dsPIC30F4011/4012 19.4.6.3 Receive Error Interrupts A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt Status register, C1INTF. • Invalid message received. • If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. • Receiver overrun. • The RXxOVR bit indicates that an overrun condition occurred.
dsPIC30F4011/4012 19.5.6 19.6 TRANSMIT INTERRUPTS Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt • • • • • • At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
dsPIC30F4011/4012 19.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64 in addition to a fixed divide-by-2 for clock generation. The Time Quantum (TQ) is a fixed unit of time derived from the oscillator period, shown in Equation 19-1, where FCAN is FCY (if the CANCKS bit is set) or 4 FCY (if CANCKS is cleared). Note: FCAN must not exceed 30 MHz. If CANCKS = 0, FCY must not exceed 7.5 MHz.
CAN1 REGISTER MAP(1) SFR Name Addr.
© 2010 Microchip Technology Inc. TABLE 19-1: SFR Name C1TX1B2 Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 138 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 20.0 Note: 10-BIT, HIGH-SPEED ANALOGTO-DIGITAL CONVERTER (ADC) MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 FIGURE 20-1: 10-BIT, HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM AVDD VREF+ AVSS VREF- AN2 + AN6 - AN1 AN4 + AN7 - S/H CH1 ADC 10-bit Result S/H Conversion Logic CH2 16-word, 10-bit Dual Port Buffer AN2 AN5 + AN8 - S/H CH3 CH1,CH2, CH3,CH0 Sample AN3 AN0 AN1 AN2 AN3 AN4 AN4 AN5 AN5 AN6(1) AN6 AN7(1) AN7 AN8(1) AN8 + AN1 - Input Switches S/H Sample/Sequence Control Bus Interface AN1 AN0 AN3 Data Format AN0 Input MUX Control CH0 Note 1: Not availa
dsPIC30F4011/4012 20.1 A/D Result Buffer The module contains a 16-word, dual port, read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 10 bits wide, but is read into different format 16-bit words. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 20.2 Conversion Operation After the ADC module has been configured, the sample acquisition is started by setting the SAMP bit.
dsPIC30F4011/4012 20.4 Programming the Start of the Conversion Trigger The conversion trigger terminates acquisition and starts the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit causes the conversion trigger.
dsPIC30F4011/4012 20.7 A/D Conversion Speeds The dsPIC30F 10-bit ADC specifications permit a maximum 1 Msps sampling rate. Table 20-1 summarizes the conversion speeds for the dsPIC30F 10-bit ADC and the required operating conditions. TABLE 20-1: 10-BIT A/D CONVERSION RATE PARAMETERS dsPIC30F 10-bit A/D Converter Conversion Rates A/D Speed Up to 1 Msps(1) TAD Sampling RS Max. Minimum Time Min. 83.33 ns 12 TAD 500Ω VDD Temperature 4.5V to 5.
dsPIC30F4011/4012 The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external VREF pins usage and there are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. Figure 20-2 illustrates the recommended circuit for the conversion rates above 500 ksps.
dsPIC30F4011/4012 20.7.1.3 1 Msps Configuration Items The following configuration items are required to achieve a 1 Msps conversion rate.
dsPIC30F4011/4012 20.8 A/D Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 20-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device VDD and the holding capacitor charge time. For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
dsPIC30F4011/4012 20.9 Module Power-Down Modes If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the ADC module is then turned off, although the ADON bit remains set. The module has 3 internal power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings.
dsPIC30F4011/4012 20.13 Configuring Analog Port Pins 20.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) is converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
© 2010 Microchip Technology Inc. TABLE 20-2: SFR Name ADC REGISTER MAP(1) Addr.
dsPIC30F4011/4012 NOTES: DS70135G-page 150 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 21.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL Description 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal EC External clock input (0-40 MHz) ECIO External clock input (0-40 MHz), OSC2 pi
dsPIC30F4011/4012 FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<1:0> Primary Osc NOSC<1:0> Primary Oscillator Stability Detector POR Done OSWEN Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector Programmable Clock Divider System Clock 2 POST<1:0> FRC Internal Fast RC O
dsPIC30F4011/4012 21.2 Oscillator Configurations 21.2.1 21.2.2 INITIAL CLOCK SOURCE SELECTION In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer (OST) is included. It is a simple, 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The timeout period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e.
dsPIC30F4011/4012 21.2.3 LP OSCILLATOR CONTROL Enabling the LP oscillator is controlled with two elements: • Current oscillator group bits, COSC<1:0> • LPOSCEN bit (OSCCON<1>) The LP oscillator is on (even during Sleep mode) if LPOSCEN = 1. The LP oscillator is the device clock if: • COSC<1:0> = 00 (LP selected as main osc.) and • LPOSCEN = 1 Keeping the LP oscillator on at all times allows for a fast switch to the 32 kHz system clock for lower power operation.
dsPIC30F4011/4012 21.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM<1:0> Configuration bits (Clock Switch and Monitor Selection bits) in the FOSC device Configuration register. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the SWDTEN bit.
dsPIC30F4011/4012 21.3 Reset 21.3.
dsPIC30F4011/4012 FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 21-5: VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET DS70135G-page 158 © 2010 Microchip Technology
dsPIC30F4011/4012 21.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially lowfrequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: A BOR generates a Reset pulse, which resets the device.
dsPIC30F4011/4012 Table 21-5 lists the Reset conditions for the RCON Register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column.
dsPIC30F4011/4012 21.4 21.4.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free-running timer that runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer continues to operate even if the main processor clock (e.g., the crystal oscillator) fails. 21.4.
dsPIC30F4011/4012 Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level can wake-up the processor. The processor processes the interrupt and branches to the ISR. The SLEEP status bit in the RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out (e.g., for low-frequency crystals).
dsPIC30F4011/4012 21.7 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. When the device has this feature enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. one of four pairs of debug I/O pins may be selected by the user using configuration options in MPLAB IDE.
SFR Name Addr. Bit 15 Bit 14 Bit 13 RCON 0740 TRAPR IOPUWR BGST OSCCON 0742 Legend: Note 1: TUN3 Bit 11 Bit 10 Bit 9 Bit 8 TUN1 TUN0 NOSC<1:0> — COSC<1:0> Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXTR SWR SWDTEN WDTO SLEEP IDLE LOCK — CF — POST<1:0> Bit 1 Bit 0 BOR POR Reset State Depends on type of Reset. LPOSCEN OSWEN Depends on Configuration bits.
dsPIC30F4011/4012 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Reference Manual” (DS70157).
dsPIC30F4011/4012 Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP.
dsPIC30F4011/4012 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Wb Wd Wdo Wm,Wn Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx Wxd Wy Wyd © 2010 Microchip Technology Inc. Description Base W register ∈ {W0..
dsPIC30F4011/4012 TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Mnemonic # 1 2 3 4 5 6 7 8 ADD ADDC AND ASR BCLR BRA BSET BSW Assembly Syntax Description # of words # of cycles Status Flags Affected ADD Acc Add Accumulators 1 1 OA, OB, SA, SB ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd =
dsPIC30F4011/4012 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 9 10 11 12 13 14 15 BTG BTSC BTSS BTST BTSTS CALL CLR Assembly Syntax Description # of words # of cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 BTG Ws,#bit4 Bit Toggle Ws 1 1 None None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) No
dsPIC30F4011/4012 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 29 DIV Assembly Syntax Description # of words # of cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.
dsPIC30F4011/4012 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 48 MPY Assembly Syntax Description # of words # of cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA, OB, OAB, SA, SB, SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA, OB, OAB, SA, SB, SAB -(Multiply Wm by Wn) to Accumulator 1 1 None 1 1 OA, OB, OAB, SA, SB, SAB 49 MPY.N MPY.
dsPIC30F4011/4012 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 66 RRNC Assembly Syntax Description # of words # of cycles Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC30F4011/4012 23.
dsPIC30F4011/4012 23.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 23.
dsPIC30F4011/4012 23.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC30F4011/4012 23.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 23.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC30F4011/4012 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
dsPIC30F4011/4012 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30F401X-30I dsPIC30F401X-20E 30 — 20 4.5-5.5V -40°C to +85°C 4.5-5.5V -40°C to +125°C — 3.0-3.6V -40°C to +85°C 20 — 3.0-3.6V -40°C to +125°C — 15 2.5-3.
dsPIC30F4011/4012 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Min Typ(1) Max Units Conditions Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.
dsPIC30F4011/4012 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC30F4011/4012 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1,2) Max Units Conditions Operating Current (IDD)(3) DC51a 1.3 3 mA +25°C DC51b 1.3 3 mA +85°C DC51c 1.3 3 mA +125°C DC51e 2.7 5 mA +25°C DC51f 2.7 5 mA +85°C DC51g 2.
dsPIC30F4011/4012 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC60a 0.3 — μA 25°C DC60b 1 30 μA 85°C DC60c 12 60 μA 125°C DC60e 0.
dsPIC30F4011/4012 TABLE 24-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
dsPIC30F4011/4012 TABLE 24-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VOL DO10 Characteristic VOH Typ(1) Max Units Conditions Output Low Voltage(2) I/O ports DO16 Min — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V OSC2/CLKO — — 0.6 V IOL = 1.
dsPIC30F4011/4012 TABLE 24-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. Symbol BO10 VBOR BO15 Characteristic BOR Voltage on VDD Transition High-to-Low(2) Min 2: 3: Max Units Conditions Not in operating range BORV = 11(3) — — — V BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.
dsPIC30F4011/4012 24.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Section 24.1 “DC Characteristics”.
dsPIC30F4011/4012 TABLE 24-13: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic Min Typ(1) Max Units External CLKI Frequency (external clocks allowed only in EC mode)(2) DC 4 4 4 — — — — 40 10 10 7.5 MHz MHz MHz MHz EC EC with 4x PLL EC with 8x PLL EC with 16x PLL Oscillator Frequency(2) DC 0.
dsPIC30F4011/4012 TABLE 24-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units — — — — — — 10 10 7.5(3) 10 10 7.
dsPIC30F4011/4012 TABLE 24-16: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator Mode FOSC (MHz)(1) TCY (μsec)(2) MIPS w/o PLL(3) MIPS w/PLL x4(3) MIPS w/PLL x8(3) MIPS w/PLL x16(3) EC 0.200 20.0 0.05 — — — XT Note 1: 2: 3: 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Assumption: Oscillator postscaler is divide by 1. Instruction Execution Cycle Time: TCY = 1/MIPS.
dsPIC30F4011/4012 TABLE 24-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 Note 1: FRC — — ±2.00 % -40°C ≤TA ≤+85°C VDD = 3.0-5.5V — — ±5.00 % -40°C ≤TA ≤+125°C VDD = 3.0-5.5V Frequency calibrated at 7.
dsPIC30F4011/4012 FIGURE 24-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to the Figure 24-2 for load. TABLE 24-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 FIGURE 24-5: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out Oscillator Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to the Figure 24-2 for load conditions. DS70135G-page 192 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 TABLE 24-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F4011/4012 FIGURE 24-7: TIMERx EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 24-2 for load conditions. TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 TABLE 24-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 TB20 Symbol TTXH TTXL TTXP Characteristic TxCK High Time TxCK Low Time TxCK Input Period Min Typ Max Units Conditions Synchronous, no prescaler 0.
dsPIC30F4011/4012 FIGURE 24-8: QEI MODULE EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 FIGURE 24-9: INPUT CAPTURE TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 24-2 for load conditions. TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 FIGURE 24-10: OUTPUT COMPARE MODULE TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 24-2 for load conditions. TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 2.5V to 5.
dsPIC30F4011/4012 FIGURE 24-11: OUTPUT COMPARE/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx TABLE 24-28: SIMPLE OUTPUT COMPARE/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F4011/4012 FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA MP20 PWMx FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-2 for load conditions. TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 2.5V to 5.
dsPIC30F4011/4012 FIGURE 24-14: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F4011/4012 FIGURE 24-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F4011/4012 FIGURE 24-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCK1 (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCK1 (CKP = 1) SP35 SP31 SDI1 LSb Bit 14 - - - - - -1 MSb SDO1 SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F4011/4012 FIGURE 24-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK1 (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCK1 (CKP = 1) SP35 SP40 SDI1 LSb Bit 14 - - - - - -1 MSb SDO1 SP30,SP31 Bit 14 - - - -1 MSb In LSb In SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F4011/4012 FIGURE 24-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS1 SP52 SP50 SCK1 (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCK1 (CKP = 1) SP35 SDO1 MSb Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDI1 SDI MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-2 for load conditions. © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 TABLE 24-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 FIGURE 24-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS1 SP52 SP50 SCK1 (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCK1 (CKP = 1) SP35 SP52 MSb SDO1 Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDI1 MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-2 for load conditions. © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 TABLE 24-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 FIGURE 24-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 24-2 for load conditions. FIGURE 24-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure 24-2 for load conditions. © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 TABLE 24-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) I Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F4011/4012 FIGURE 24-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 24-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 TABLE 24-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 Symbol TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT Characteristic Clock Low Time Clock High Time SDA and SCL Fall Time SDA and SCL Rise Time Data Input Setup Time Min Max Units 100 kHz mode 4.
dsPIC30F4011/4012 FIGURE 24-24: C1TX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 C1RX Pin (input) CA20 TABLE 24-38: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F4011/4012 TABLE 24-39: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
dsPIC30F4011/4012 TABLE 24-39: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Min. Typ Max.
dsPIC30F4011/4012 FIGURE 24-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 8 9 5 6 8 9 1 - Software sets ADCONx. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17.
dsPIC30F4011/4012 FIGURE 24-26: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 TCONV AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADCONx. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period.
dsPIC30F4011/4012 TABLE 24-40: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ Max.
dsPIC30F4011/4012 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example dsPIC30F401230I/SP e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP 0710017 Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC30F4011/4012 Package Marking Information (Continued) 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70135G-page 220 Example dsPIC30F 4012-30I/ ML e3 0710017 Example dsPIC30F 4011-30I/ PT e3 0710017 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 25.2 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .
dsPIC30F4011/4012 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
dsPIC30F4011/4012 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .
dsPIC30F4011/4012 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.
dsPIC30F4011/4012 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC30F4011/4012 NOTES: DS70135G-page 226 © 2010 Microchip Technology Inc.
dsPIC30F4011/4012 APPENDIX A: REVISION HISTORY Revision D (August 2006) Previous versions of this data sheet contained Advance or Preliminary Information. They were distributed with incomplete characterization data. This revision reflects these changes: • Revised I2C Slave Addresses (see Table 17-1) • Updated Section 20.
dsPIC30F4011/4012 Revision G (December 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Signal Controllers” Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”). Section 15.
dsPIC30F4011/4012 INDEX Numerics 10-Bit, High-Speed Analog-to-Digital Converter (ADC) Module ............................................................................. 137 16-bit Up/Down Position Counter Mode.............................. 90 Count Direction Status ................................................ 90 Counter Reset............................................................. 90 Error Checking ............................................................ 90 A AC Characteristics .............
dsPIC30F4011/4012 Memory Map ............................................................... 30 Near Data Space ........................................................ 33 Software Stack ............................................................ 33 Width ........................................................................... 32 Data EEPROM Memory ...................................................... 55 Erasing ........................................................................
dsPIC30F4011/4012 M Operating MIPS vs. Voltage.............................................. 176 Oscillator Configurations........................................................... 152 Fail-Safe Clock Monitor .................................... 154 Fast RC (FRC) .................................................. 153 Initial Clock Source Selection ........................... 152 Low-Power RC (LPRC)..................................... 153 LP ................................................................
dsPIC30F4011/4012 S Simple Capture Event Mode Capture Buffer Operation............................................ 80 Capture Prescaler ....................................................... 80 Hall Sensor Mode ....................................................... 80 Timer2 and Timer3 Selection Mode ............................ 80 Simple Output Compare Match Mode................................. 84 Simple PWM Mode .............................................................
dsPIC30F4011/4012 U UART Address Detect Mode ............................................... 123 Alternate I/O.............................................................. 121 Auto-Baud Support ................................................... 124 Baud Rate Generator................................................ 123 Disabling ................................................................... 121 Enabling and Setting Up ........................................... 121 Loopback Mode .....................
dsPIC30F4011/4012 NOTES: DS70135G-page 234 © 2010 Microchip Technology Inc.
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