Datasheet

dsPIC30F3014/4013
DS70138G-page 60  2010 Microchip Technology Inc.
8.1 Interrupt Priority
The user-assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the
3 LSbs of each nibble within the IPCx register(s). Bit 3
of each nibble is not used and is read as a ‘0’. These
bits define the priority level assigned to a particular
interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 8-1 and Table 8-2 list the interrupt numbers,
corresponding interrupt sources and associated vector
numbers for the dsPIC30F3014 and dsPIC30F4013
devices, respectively.
The ability for the user to assign every interrupt to one
of seven priority levels means that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Pro-
grammable Low-Voltage Detect) can be given a priority
of 7. The INT0 (External Interrupt 0) may be assigned
to priority Level 1, thus giving it a very low effective
priority.
TABLE 8-1: dsPIC30F3014 INTERRUPT
VECTOR TABLE
Note: The user-assignable priority levels start at
0 as the lowest priority and Level 7 as the
highest priority.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number
Vector
Number
Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC1 – Output Compare 1
3 11 T1 – Timer1
4 12 IC2 – Input Capture 2
5 13 OC2 – Output Compare 2
6 14 T2 – Timer2
7 15 T3 – Timer3
8 16 SPI1
9 17 U1RX – UART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Write Complete
13 21 SI2C – I
2
C™ Slave Interrupt
14 22 MI2C – I
2
C Master Interrupt
15 23 Input Change Interrupt
16 24 INT1 – External Interrupt 1
17-22 25-30 Reserved
23 31 INT2 – External Interrupt 2
24 32 U2RX – UART2 Receiver
25 33 U2TX – UART2 Transmitter
26 34 Reserved
27 35 C1 – Combined IRQ for CAN1
28-41 36-49 Reserved
42 50 LVD – Low-Voltage Detect
43-53 51-61 Reserved
Lowest Natural Order Priority