Datasheet

 2010 Microchip Technology Inc. DS70138G-page 125
dsPIC30F3014/4013
18.3.7 BIT CLOCK GENERATOR
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON3 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
is disabled. If the BCG<11:0> bits are set to a non-zero
value, the bit clock generator is enabled. These bits
should be set to ‘0’ and the CSCKD bit set to ‘1’ if the
serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
EQUATION 18-2: BIT CLOCK FREQUENCY
The required bit clock frequency is determined by the
system sampling rate and frame size. Typical bit clock
frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with
common audio sampling rates, the user needs to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
TABLE 18-1: DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES
FBCK =
F
CY
2 (BCG + 1)
•
FS (kHz) FCSCK/FS FCSCK (MHz)
(1)
FOSC (MHZ)PLLFCY (MIPS) BCG
(2)
8 256 2.048 8.192 4 8.192 1
12 256 3.072 6.144 8 12.288 1
32 32 1.024 8.192 8 16.384 7
44.1 32 1.4112 5.6448 8 11.2896 3
48 64 3.072 6.144 16 24.576 3
Note 1: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
operation of the DCI module.
2: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must
meet the device timing requirements.