dsPIC30F3014/4013 Data Sheet High-Performance, 16-bit Digital Signal Controllers 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC30F3014/4013 High-Performance, 16-Bit Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 CMOS Technology: • • • • Low-Power, High-Speed Flash Technology Wide Operating Voltage Range (2.5V to 5.
dsPIC30F3014/4013 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/NT1/RD8 RD2 VDD VSS RD3 IC2/INT2/RD9 INT0/RA11 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 NC 44-Pin TQFP dsPIC30F3014 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 OSC2/CLKO/RC15 OSC1/CLKI VSS VDD AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/CN7/RB5 AN4/CN6/RB4 NC NC AN10/RB10 AN9/RB9 AVSS AVDD MCLR AN0/VREF+
dsPIC30F3014/4013 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/INT1/RD8 RD2 VDD VSS RD3 IC2/INT2/RD9 INT0/RA11 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 44-Pin QFN(1) 1 2 3 4 5 6 7 8 9 10 11 dsPIC30F3014 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RC15 OSC1/CLKI VSS VSS VDD VDD AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/CN7/RB5 AN4/CN6/RB4 AN11/RB11 NC AN10/RB10 AN9/RB9 AVSS AVDD MCLR AN0/VREF+/CN2/RB0 AN1/VREF-/CN3
dsPIC30F3014/4013 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/INT1/RD8 OC3/RD2 VDD VSS OC4/RD3 IC2/INT2/RD9 INT0/RA11 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 NC 44-Pin TQFP dsPIC30F4013 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 OSC2/CLKO/RC15 OSC1/CLKI VSS VDD AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 NC NC AN10/CSDI/RB10 AN9/CSCK/R
dsPIC30F3014/4013 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/NT1/RD8 OC3/RD2 VDD VSS OC4/RD3 IC2/INT2/RD9 INT0/RA11 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 44-Pin QFN(1) 1 2 3 4 5 6 7 8 9 10 11 dsPIC30F4013 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RC15 OSC1/CLKI VSS VSS VDD VDD AN8/RB8 PGD/EMUD/AN7/RB7 PGC/EMUC/AN6/OCFA/RB6 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN11/CSDO/RB11 NC AN10/CSDI/RB10 AN9/CSCK/RB9 AVSS AVDD MCLR A
dsPIC30F3014/4013 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 CPU Architecture Overview........................................................................................................................................................ 15 3.0 Memory Organization ...........................................................................
dsPIC30F3014/4013 NOTES: DS70138G-page 10 2010 Microchip Technology Inc.
dsPIC30F3014/4013 1.0 DEVICE OVERVIEW Note: This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013, respectively.
dsPIC30F3014/4013 FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 Data Latch Y Data RAM (1 Kbyte) Address Latch 16 24 Program Memory (48 Kbytes) INT0/RA11 PORTA 16 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Data Latch X Data RAM (1 Kbyte) Address Latch 16 16 24 Address Latch 16 16 AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/R
dsPIC30F3014/4013 Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN12 I Analog Analog input channels. AN6 and AN7 are also used for device programming data and clock inputs, respectively.
dsPIC30F3014/4013 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type RA11 I/O ST PORTA is a bidirectional I/O port. RB0-RB12 I/O ST PORTB is a bidirectional I/O port. RC13-RC15 I/O ST PORTC is a bidirectional I/O port. RD0-RD3, RD8, RD9 I/O ST PORTD is a bidirectional I/O port. Pin Name Description RF0-RF5 I/O ST PORTF is a bidirectional I/O port. SCK1 SDI1 SDO1 SS1 I/O I O I ST ST — ST Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out.
dsPIC30F3014/4013 2.0 Note: 2.1 CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 The core does not support a multi-stage instruction pipeline. However, a single-stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors.
dsPIC30F3014/4013 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC30F3014/4013 2.3 Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. 2. 3. 4. 5. DIVF – 16/16 signed fractional divide DIV.sd – 32/16 signed divide DIV.ud – 32/16 unsigned divide DIV.s – 16/16 signed divide DIV.
dsPIC30F3014/4013 2.4 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.
dsPIC30F3014/4013 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70138G-page 20 2010 Microchip Technology Inc.
dsPIC30F3014/4013 2.4.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value, which is signextended to 40 bits.
dsPIC30F3014/4013 The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. When saturation is not enabled, SA and SB default to bit 39 overflow and, thus, indicate that a catastrophic overflow has occurred.
dsPIC30F3014/4013 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.
dsPIC30F3014/4013 NOTES: DS70138G-page 24 2010 Microchip Technology Inc.
dsPIC30F3014/4013 Note: MEMORY ORGANIZATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> Instruction Access User TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA<15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA<15:0> Program Space Visibility User FIGURE 3-3: <0> PC<22:1> 0 0 PSVPAG<7:0> 0 Data EA<14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Us
dsPIC30F3014/4013 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word-sized data to and from program space. (See Figure 3-4 and Figure 3-5.) 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
dsPIC30F3014/4013 FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
dsPIC30F3014/4013 FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x0000 0x000100 PSVPAG(1) 0x00 8 15 EA<15> = 0 Data 16 Space 15 EA EA<15> = 1 0x8000 15 Address Concatenation 23 23 15 0 0x000200 Upper Half of Data Space is Mapped into Program Space 0x007FFF 0xFFFF BSET MOV MOV MOV CORCON,#2 #0x00, W0 W0, PSVPAG 0x8200, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit
dsPIC30F3014/4013 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 3.2.1 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space.
dsPIC30F3014/4013 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-8: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W 2010 Microchip Technology Inc.
dsPIC30F3014/4013 3.2.2 DATA SPACES 3.2.3 The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.
dsPIC30F3014/4013 All byte loads into any W register are loaded into the LSB. The MSB is not modified. A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address.
SFR Name CORE REGISTER MAP(1) Address (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
dsPIC30F3014/4013 NOTES: DS70138G-page 36 2010 Microchip Technology Inc.
dsPIC30F3014/4013 4.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
dsPIC30F3014/4013 4.2.1 START AND END ADDRESS 4.2.2 The Modulo Addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses.
dsPIC30F3014/4013 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
dsPIC30F3014/4013 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1
dsPIC30F3014/4013 NOTES: DS70138G-page 42 2010 Microchip Technology Inc.
dsPIC30F3014/4013 5.0 FLASH PROGRAM MEMORY Note: 5.2 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 5.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the Table Pointer must be changed at each panel boundary.
dsPIC30F3014/4013 5.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. 5.6.1 4. 5.
dsPIC30F3014/4013 5.6.3 LOADING WRITE LATCHES 5.6.4 Example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 5-2: INITIATING THE PROGRAMMING SEQUENCE For protection, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed.
2010 Microchip Technology Inc. NVM REGISTER MAP(1) TABLE 5-1: File Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 48 2010 Microchip Technology Inc.
dsPIC30F3014/4013 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 6.2 6.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example 6-2. EXAMPLE 6-2: 6.2.2 ERASING A WORD OF DATA EEPROM The NVMADRU and NVMADR registers must point to the block.
dsPIC30F3014/4013 6.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase the data EEPROM word. a) Select the word, data EEPROM erase and set the WREN bit in the NVMCON register. b) Write the address of word to be erased into NVMADR. c) Enable the NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This begins the erase cycle. g) Either poll the NVMIF bit or wait for the NVMIF interrupt.
dsPIC30F3014/4013 EXAMPLE 6-5: 6.
dsPIC30F3014/4013 7.0 Note: I/O PORTS Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F3014/4013 FIGURE 7-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Output Multiplexers Peripheral Module Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Output Enable 0 Peripheral Output Data 1 PIO Module Output Data 0 Read TRIS I/O Pad Data Bus D WR TRIS CK Q TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT 7.
2010 Microchip Technology Inc. TABLE 7-1: SFR Name Addr.
dsPIC30F3014/4013 7.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a Change-OfState (COS) on selected input pins. This module is capable of detecting input Change-Of-States, even in Sleep mode, when the clocks are disabled.
2010 Microchip Technology Inc. INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014/4013 DEVICES (BITS 15-0)(1) TABLE 7-2: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 58 2010 Microchip Technology Inc.
dsPIC30F3014/4013 8.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 8.1 Interrupt Priority The user-assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the 3 LSbs of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assignable priority levels start at 0 as the lowest priority and Level 7 as the highest priority.
dsPIC30F3014/4013 TABLE 8-2: dsPIC30F4013 INTERRUPT VECTOR TABLE Interrupt Vector Number Number Interrupt Source Highest Natural Order Priority 8.2 Reset Sequence A Reset is not a true exception because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000.
dsPIC30F3014/4013 8.3 Address Error Trap: Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1. They are intended to provide the user a means to correct erroneous operation during debug and when operating within the application.
dsPIC30F3014/4013 Each hard trap that occurs must be Acknowledged before code execution of any type may continue. If a lower priority hard trap occurs while a higher priority trap is pending, Acknowledged, or is being processed, a hard trap conflict occurs. The device is automatically Reset in a hard trap conflict condition. The TRAPR status bit (RCON<15>) is set when the Reset occurs so that the condition may be detected in software.
dsPIC30F3014/4013 8.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 8-1. Access to the alternate vector table is provided by the ALTIVT bit in the INTCON2 register. If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors.
2010 Microchip Technology Inc.
SFR Name ADR dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — — — C1IF U1TXIF U1RXIF — U2TXIF LVDIF DCIIF IFS2 0088 — — — — — IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE IE
dsPIC30F3014/4013 9.0 Note: TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F3014/4013 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON<6>), must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). When the CPU goes into the Idle mode, the timer stops incrementing unless TSIDL = 0.
2010 Microchip Technology Inc. TABLE 9-1: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 70 2010 Microchip Technology Inc.
dsPIC30F3014/4013 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored.
dsPIC30F3014/4013 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 PR2 0 T3IF Event Flag 1 Q D Q CK TGATE (T2CON<6>) TCS TGATE TGATE (T2CON<6>) TON T2CK Note: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer Configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation.
dsPIC30F3014/4013 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Reset T2IF Event Flag Comparator x 16 TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE TON T2CK TCKPS<1:0> 2 1x FIGURE 10-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 1 Q D Q CK TGATE T3CK TGATE TCS TGATE T3IF Event Flag Sync TON 1x 01 TCY Note: TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 T3CK pin does not exist on dsPIC3
dsPIC30F3014/4013 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
2010 Microchip Technology Inc. TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP(1) SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 76 2010 Microchip Technology Inc.
dsPIC30F3014/4013 11.0 Note: TIMER4/5 MODULE The Timer4/5 module is similar in operation to the Timer2/3 module. However, there are some differences: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046).
dsPIC30F3014/4013 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Reset TMR4 Sync 0 1 Q D Q CK TGATE TCS TGATE T4IF Event Flag Comparator x 16 TGATE TON T4CK FIGURE 11-3: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Reset TMR5 0 1 Q D Q CK TGATE TCS TGATE T5IF Event Flag Comparator x 16 TGATE T5CK TON Sync 1x 01 TCY Note: TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 In the dsPIC30F3014 device, th
2010 Microchip Technology Inc. TABLE 11-1: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 80 2010 Microchip Technology Inc.
dsPIC30F3014/4013 12.0 INPUT CAPTURE MODULE Note: These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain up to 8 capture channels (i.e., the maximum value of N is 8). The dsPIC30F3014 device contains 2 capture channels while the dsPIC30F4013 device contains 4 capture channels. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F3014/4013 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE is set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer.
2010 Microchip Technology Inc. TABLE 12-1: SFR Name Addr. IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 Legend: Note 1: Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 84 2010 Microchip Technology Inc.
dsPIC30F3014/4013 13.0 Note: OUTPUT COMPARE MODULE These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC DSC devices contain up to 8 compare channels (i.e., the maximum value of N is 8). The dsPIC30F3014 device contains 2 compare channels while the dsPIC30F4013 device contains 4 compare channels. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F3014/4013 13.2 Simple Output Compare Match Mode When control bits, OCM<2:0> (OCxCON<2:0>) = 001, 010 or 011, the selected output compare channel is configured for one of three simple Output Compare Match modes: 13.3.2 CONTINUOUS PULSE MODE For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required: The OCxR register is used in these modes.
dsPIC30F3014/4013 13.4.2 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1. EQUATION 13-1: PWM period = [(PRx) + 1] • 4 • TOSC • (TMRx prescale value) PWM frequency is defined as 1/[PWM period]. When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set.
dsPIC30F3014/4013 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel drives the pin to the active state that was observed prior to entering the CPU Sleep state. For example, if the pin was high when the CPU entered the Sleep state, the pin remains high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin remains low.
2010 Microchip Technology Inc. TABLE 13-1: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 90 2010 Microchip Technology Inc.
dsPIC30F3014/4013 14.0 Note: I2C™ MODULE 14.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the 'dsPIC30F Family Reference Manual' (DS70046).
dsPIC30F3014/4013 FIGURE 14-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70138G-page 92 Write I2CBRG FCY Read 2010 Microchip Technology Inc.
dsPIC30F3014/4013 14.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 LSbs of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
dsPIC30F3014/4013 14.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 14.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 14.5.
dsPIC30F3014/4013 14.7 Interrupts The I2C module generates two interrupt flags, MI2CIF (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 14.8 Slope Control 2 The I C standard requires slope control on the SDA and SCL signals for Fast mode (400 kHz).
dsPIC30F3014/4013 14.12.2 I2C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<3>). The I2C module must be Idle before the RCEN bit is set; otherwise, the RCEN bit is disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin ACK and data are shifted into the I2CRSR on the rising edge of each clock.
2010 Microchip Technology Inc. TABLE 14-2: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 98 2010 Microchip Technology Inc.
dsPIC30F3014/4013 15.0 Note: SPI MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI) module is a synchronous serial interface.
dsPIC30F3014/4013 15.2 Framed SPI Support the SSx pin is an input or an output (i.e., whether the module receives or generates the Frame Synchronization pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When Frame Synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. The module supports a basic framed SPI protocol in Master or Slave mode.
dsPIC30F3014/4013 15.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset.
SFR Name dsPIC30F3014/4013 SPI1 REGISTER MAP Addr. Bit 15 Bit 14 Bit 13 Bit 12 SPIEN — SPISIDL — — FRMEN SPIFSD — Bit 11 Bit 10 SPI1STAT 0220 SPI1CON 0222 — — SPI1BUF 0224 Legend: Note 1: — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013 16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 16.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F3014/4013 FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE Write UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters UxRX or UxARX if ALTIO = 1 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Load RSR to Buffer Receive Shift Register (UxRSR) Control Signals FERR 0 8-9 PERR LPBACK From UxTX 1 16 Divider 16x Baud Clock from Baud Rate Generat
dsPIC30F3014/4013 16.2 16.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input, respectively, overriding the TRIS and LAT register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 16.2.2 16.3 16.3.1 Disabling the UART module resets the buffers to empty states.
dsPIC30F3014/4013 16.3.4 TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This means that the transmit buffer has at least one empty word.
dsPIC30F3014/4013 16.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’; otherwise, FERR is set. The readonly FERR bit is buffered along with the received data; it is cleared on any Reset. 16.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
dsPIC30F3014/4013 16.9 Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 16.10.2 UART OPERATION DURING CPU IDLE MODE For the UART, the USIDL bit determines if the module stops or continues operation when the device enters Idle mode.
2010 Microchip Technology Inc. TABLE 16-1: dsPIC30F3014/4013 UART1 REGISTER MAP(1) SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 110 2010 Microchip Technology Inc.
dsPIC30F3014/4013 17.0 Note: 17.1 CAN MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). Overview The CAN bus module consists of a protocol engine and message buffering/control.
dsPIC30F3014/4013 FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1(2) BUFFERS Acceptance Filter RXF2(2) TXB2(2) TXREQ TXABT TXLARB TXERR MESSAGE TXREQ TXABT TXLARB TXERR MESSAGE TXB1(2) TXREQ TXABT TXLARB TXERR MESSAGE TXB0(2) A c c e p t Acceptance Mask RXM0(2) Acceptance Filter RXF3(2) Acceptance Filter RXF0(2) Acceptance Filter RXF4(2) Acceptance Filter RXF1(2) Acceptance Filter RXF5(2) R(2) X B 0 Message Queue Control Transmit Byte Sequencer Identifier M
dsPIC30F3014/4013 17.3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).
dsPIC30F3014/4013 17.4 17.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, denoted as RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
dsPIC30F3014/4013 • Receive Error Interrupts: A receive error interrupt is indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error is indicated by the IVRIF bit. - Receiver Overrun: The RXnOVR bit indicates that an overrun condition occurred.
dsPIC30F3014/4013 17.5.6 TRANSMIT INTERRUPTS 17.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
dsPIC30F3014/4013 17.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64 in addition to a fixed divide-by-2 for clock generation. The Time Quantum (TQ) is a fixed unit of time derived from the oscillator period, shown in Equation 17-1, where FCAN is FCY (if the CANCKS bit is set) or 4FCY (if CANCKS is clear). Note: FCAN must not exceed 30 MHz. If CANCKS = 0, then FCY must not exceed 7.5 MHz.
SFR Name dsPIC30F4013 CAN1 REGISTER MAP(1) Addr.
2010 Microchip Technology Inc. TABLE 17-1: SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 120 2010 Microchip Technology Inc.
dsPIC30F3014/4013 18.0 Note: 18.1 DATA CONVERTER INTERFACE (DCI) MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F3014/4013 FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word-Size Selection bits Frame Length Selection bits 16-Bit Data Bus DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70138G-page 122 2010 Microchip Technology Inc.
dsPIC30F3014/4013 18.3 18.3.1 DCI Module Operation MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, Frame Sync, and the DCI buffer control unit are reset. The DCI clocks are shut down when the DCIEN bit is cleared.
dsPIC30F3014/4013 size and Frame Sync generator control bits. A new I2S data transfer boundary is marked by a high-to-low or a low-to-high transition edge on the COFS pin. 18.3.6 SLAVE FRAME SYNC OPERATION When the DCI module is operating as a Frame Sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals.
dsPIC30F3014/4013 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock is disabled. If the BCG<11:0> bits are set to a non-zero value, the bit clock generator is enabled.
dsPIC30F3014/4013 18.3.8 SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data is sampled on the falling edge of the CSCK signal. The AC-Link protocols and most multichannel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data is sampled on the rising edge of CSCK.
dsPIC30F3014/4013 18.3.14 BUFFER LENGTH CONTROL The amount of data that is buffered between interrupts is determined by the buffer length (BLEN<1:0>) control bits in the DCICON2 SFR. The size of the transmit and receive buffers may be varied from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter. When the two LSbs of the DCI address counter match the BLEN<1:0> value, the buffer control unit is reset to ‘0’.
dsPIC30F3014/4013 18.3.18 SLOT STATUS BITS 18.4 The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits correspond to the value of the Frame Sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 18.3.
dsPIC30F3014/4013 18.6.2 20-BIT AC-LINK MODE The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF registers. The 20-bit AC-Link mode functions similar to the Multichannel mode of the DCI module, except for the duty cycle of the Frame Synchronization signal. The ACLink Frame Synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles.
dsPIC30F3014/4013 DCI REGISTER MAP(1) SFR Name Addr.
dsPIC30F3014/4013 19.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Note: The A/D module has six 16-bit registers: • • • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The ADCON1, ADCON2 and ADCON3 registers control the operation of the A/D module.
dsPIC30F3014/4013 19.1 A/D Result Buffer The module contains a 16-word, dual port read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 19.
dsPIC30F3014/4013 19.4 Programming the Start of Conversion Trigger The conversion trigger terminates acquisition and starts the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to 4 alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit causes the conversion trigger. When SSRC<2:0> = 111 (Auto-Convert mode), the conversion trigger is under A/D clock control.
dsPIC30F3014/4013 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-Bit ADC Conversion Rates Speed Up to 200 ksps(1) TAD Sampling Minimum Time Min 334 ns 1 TAD Rs Max VDD Temperature 2.5 k 4.5V to 5.
dsPIC30F3014/4013 Figure 19-2 depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F3014 is shown as an example. 35 34 37 36 38 See Note 1 1 33 2 32 VSS 31 VSS 30 3 4 5 dsPIC30F3014 6 VSS 7 VDD 8 VDD 9 C8 1 F VDD C7 0.1 F VDD C6 0.01 F VDD 25 24 23 AVDD C5 1 F AVDD C4 0.1 F AVDD C3 0.
dsPIC30F3014/4013 FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP = 1 TAD TSAMP = 1 TAD ADCLK TCONV = 14 TAD TCONV = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 A/D Acquisition Requirements The analog input model of the 12-bit A/D converter is shown in Figure 19-4. The total sampling time for the A/D is a function of the internal amplifier settling time and the holding capacitor charge time.
dsPIC30F3014/4013 19.9 Module Power-Down Modes The module has two internal power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings. In order to return to the Active mode from Off mode, the user must wait for the ADC circuitry to stabilize. The time required to stabilize is specified in Section 23.
dsPIC30F3014/4013 19.13 Configuring Analog Port Pins 19.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) is converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
2010 Microchip Technology Inc. TABLE 19-2: A/D CONVERTER REGISTER MAP(1) SFR Name Addr.
dsPIC30F3014/4013 NOTES: DS70138G-page 140 2010 Microchip Technology Inc.
dsPIC30F3014/4013 20.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 400 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.
dsPIC30F3014/4013 FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request OSC1 OSC2 FPLL Primary Oscillator PLL PLL x4, x8, x16 Lock COSC<2:0> Primary Osc NOSC<2:0> Primary Oscillator OSWEN Stability Detector POR Done Oscillator Start-up Timer Clock Secondary Osc SOSCO SOSCI 32 kHz LP Oscillator Switching and Control Block Secondary Oscillator Stability Detector Programmable Clock Divider System Clock 2 POST<1:0> TUN<3:0> 4 Internal
dsPIC30F3014/4013 20.2 20.2.2 Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer is included. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e.
dsPIC30F3014/4013 20.2.3 LP OSCILLATOR CONTROL Enabling the LP oscillator is controlled with two elements: • The current oscillator group bits, COSC<2:0>. • The LPOSCEN bit (OSCCON register). The LP oscillator is on (even during Sleep mode) if LPOSCEN = 1. The LP oscillator is the device clock if: • COSC<2:0> = 00 (LP selected as main osc.) and • LPOSCEN = 1 Keeping the LP oscillator on at all times allows for a fast switch to the 32 kHz system clock for lower power operation.
dsPIC30F3014/4013 20.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the SWDTEN bit.
dsPIC30F3014/4013 20.3 Oscillator Control Registers The oscillators are controlled with two SFRs, OSCCON and OSCTUN and one Configuration register, FOSC. Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Configuration register provided in this section are applicable only to the dsPIC30F3014 and dsPIC30F4013 devices in the dsPIC30F product family.
dsPIC30F3014/4013 REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when PLL lock is achieved after a PLL start. Reset when lock is lost.
dsPIC30F3014/4013 REGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 TUN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 TUN<3:0>: TUN Field Lower Two bits The four-bit field specified by TU
dsPIC30F3014/4013 REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER U U U U U U U U — — — — — — — — bit 23 bit 16 R/P R/P FCKSM<1:0> U U U — — — R/P R/P R/P FOS<2:0> bit 15 bit 8 U U U — — — R/P R/P R/P R/P R/P FPR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock
dsPIC30F3014/4013 20.
dsPIC30F3014/4013 FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 20-5: VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70138G-page 152 2010 Microchip Technolog
dsPIC30F3014/4013 20.4.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially lowfrequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used).
dsPIC30F3014/4013 Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column.
dsPIC30F3014/4013 20.5 20.5.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free-running timer that runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer continues to operate even if the main processor clock (e.g., the crystal oscillator) fails. 20.5.
dsPIC30F3014/4013 Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level can wake-up the processor. The processor processes the interrupt and branch to the ISR. The SLEEP status bit in the RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out (e.g., for low-frequency crystals).
dsPIC30F3014/4013 20.9 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled so writes to those registers have no effect and read values are invalid.
SFR Name Addr.
dsPIC30F3014/4013 21.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F3014/4013 Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP.
dsPIC30F3014/4013 TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register {W0..
dsPIC30F3014/4013 TABLE 21-2: Base Instr # 1 2 3 4 5 6 7 8 INSTRUCTION SET OVERVIEW Assembly Mnemoni c ADD ADDC AND ASR BCLR BRA BSET BSW Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC
dsPIC30F3014/4013 TABLE 21-2: Base Instr # 9 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemoni c BTG BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4
dsPIC30F3014/4013 TABLE 21-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemoni c DIV Assembly Syntax Description # of # of Words Cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC30F3014/4013 TABLE 21-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemoni c MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC30F3014/4013 TABLE 21-2: Base Instr # 66 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemoni c RRNC Assembly Syntax Description # of # of Words Cycles Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC30F3014/4013 22.
dsPIC30F3014/4013 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 22.
dsPIC30F3014/4013 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC30F3014/4013 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC30F3014/4013 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
dsPIC30F3014/4013 23.1 DC Characteristics TABLE 23-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30FXXX-30I dsPIC30FXXX-20E 4.5-5.5V -40°C to 85°C 30 — 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 15 — 3.0-3.6V -40°C to 125°C — 10 2.5-3.
dsPIC30F3014/4013 TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units 2.5 — 5.5 V Industrial temperature Extended temperature Conditions Operating Voltage(2) DC10 VDD Supply Voltage DC11 VDD Supply Voltage 3.0 — 5.
dsPIC30F3014/4013 TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC30F3014/4013 TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Operating Current (IDD)(1) DC51a 1.4 3 mA 25°C DC51b 1.5 3 mA 85°C DC51c 1.
dsPIC30F3014/4013 TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC30F3014/4013 TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O Pins: with Schmitt Trigger Buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
dsPIC30F3014/4013 TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units — 0.6 V Conditions Output Low Voltage(2) VOL DO10 I/O Ports — IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKO — — 0.6 V IOL = 1.
dsPIC30F3014/4013 TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No.
dsPIC30F3014/4013 TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Min Typ(1) Max Units BORV = 11(3) — — — V BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.
dsPIC30F3014/4013 TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Table 23-1.
dsPIC30F3014/4013 TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic External CLKI Frequency (external clocks allowed only in EC mode)(2) Oscillator Frequency(2) Min Typ(1) Max Units DC 4 4 4 — — — — 40 10 10 7.
dsPIC30F3014/4013 TABLE 23-15: PLL JITTER AC CHARACTERISTICS Param No. OS61 Characteristic Min Typ(1) Max Units x4 PLL — 0.251 0.413 % -40°C TA +85°C VDD = 3.0 to 3.6V — 0.251 0.413 % -40°C TA +125°C VDD = 3.0 to 3.6V — 0.256 0.47 % -40°C TA +85°C VDD = 4.5 to 5.5V — 0.256 0.47 % -40°C TA +125°C VDD = 4.5 to 5.5V — 0.355 0.584 % -40°C TA +85°C VDD = 3.0 to 3.6V — 0.355 0.584 % -40°C TA +125°C VDD = 3.0 to 3.6V — 0.362 0.
dsPIC30F3014/4013 TABLE 23-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristic Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 Note 1: FRC — — ±2.00 % -40°C TA +85°C VDD = 3.0-5.5V — — ±5.00 % -40°C TA +125°C VDD = 3.0-5.5V Frequency calibrated at 7.
dsPIC30F3014/4013 FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 23-3 for load conditions. TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-6: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out Oscillator Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70138G-page 186 2010 Microchip Technology Inc.
dsPIC30F3014/4013 TABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F3014/4013 FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-22: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 TABLE 23-23: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.
dsPIC30F3014/4013 FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 23-3 for load conditions. TABLE 23-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-11: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F3014/4013 FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO HIGH-Z 70 CS50 LSb MSb CS30 CSDI MSb IN HIGH-Z CS31 LSb IN CS40 CS41 Note: Refer to Figure 23-3 for load conditions. DS70138G-page 192 2010 Microchip Technology Inc.
dsPIC30F3014/4013 TABLE 23-28: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS75 CS76 CS80 SDOx (CSDO) LSb MSb LSb CS76 SDIx (CSDI) CS75 MSb In CS65 CS66 DS70138G-page 194 2010 Microchip Technology Inc.
dsPIC30F3014/4013 TABLE 23-29: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.
dsPIC30F3014/4013 TABLE 23-30: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 TABLE 23-31: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 TABLE 23-32: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX Bit 14 - - - - - -1 LSb SP30,SP31 SDIX MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 23-3 for load conditions. 2010 Microchip Technology Inc.
dsPIC30F3014/4013 TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 23-3 for load conditions. FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM33 IM25 SDA In IM45 IM40 IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.
dsPIC30F3014/4013 TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. IM21 TR:SCL IM25 Min(1) Max Units 100 kHz mode — 1000 ns Characteristic SDA and SCL Rise Time TSU:DAT Data Input Setup Time 400 kHz mode 20 + 0.
dsPIC30F3014/4013 FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out 2010 Microchip Technology Inc.
dsPIC30F3014/4013 TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 FIGURE 23-22: CXTX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CXRX Pin (input) CA20 TABLE 23-36: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F3014/4013 TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.
dsPIC30F3014/4013 TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. AD24 Symbol Characteristic Min. Typ Max. Units Conditions EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error -2 -1.5 -1.
dsPIC30F3014/4013 FIGURE 23-23: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 - Software sets ADCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 18. “12-bit A/D Converter” of the dsPIC30F Family Reference Manual (DS70046). 3 - Software clears ADCON. SAMP to start conversion.
dsPIC30F3014/4013 TABLE 23-38: 12-BIT A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions VDD = 3-5.5V (Note 1) Clock Parameters AD50 TAD A/D Clock Period AD51 tRC A/D Internal RC Oscillator Period 334 — — ns 1.2 1.5 1.
dsPIC30F3014/4013 NOTES: DS70138G-page 210 2010 Microchip Technology Inc.
dsPIC30F3014/4013 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 0810017 Example 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN dsPIC 30F4013 -301/PT e3 0810017 Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC30F3014/4013 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS70138G-page 216 2010 Microchip Technology Inc.
dsPIC30F3014/4013 APPENDIX A: REVISION HISTORY Revision D (June 2006) Previous versions of this data sheet contained Advance or Preliminary Information. They were distributed with incomplete characterization data. This revision reflects these changes: • Revised I2C Slave Addresses (see Table 14-1) • Updated example for ADC Conversion Clock selection (see Section 19.
dsPIC30F3014/4013 Revision G (November 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Signal Controllers” Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”). Section 1.
dsPIC30F3014/4013 INDEX Numerics 12-Bit Analog-to-Digital Converter (A/D) Module .............. 131 A A/D .................................................................................... 131 Aborting a Conversion .............................................. 133 ADCHS Register ....................................................... 131 ADCON1 Register..................................................... 131 ADCON2 Register..................................................... 131 ADCON3 Register.......
dsPIC30F3014/4013 Round Logic ................................................................ 22 Write-Back .................................................................. 22 Data Address Space ........................................................... 30 Alignment .................................................................... 32 Alignment (Figure) ...................................................... 32 Effect of Invalid Memory Accesses (Table).................
dsPIC30F3014/4013 Transmission............................................................... 93 I2C 7-Bit Slave Mode Operation.......................................... 93 Reception.................................................................... 93 Transmission............................................................... 93 I2C Master Mode Operation ................................................ 95 Baud Rate Generator.................................................. 96 Clock Arbitration...........
dsPIC30F3014/4013 Sleep ......................................................................... 155 Power-up Timer Timing Requirements ................................................ 187 Program Address Space ..................................................... 25 Construction ................................................................ 26 Data Access from Program Memory Using Program Space Visibility........................... 28 Data Access From Program Memory Using Table Instructions ............
dsPIC30F3014/4013 CAN Module I/O........................................................ 205 CLKOUT and I/O....................................................... 185 DCI Module AC-Link Mode ................................................... 194 Multichannel, I2S Modes ................................... 192 External Clock........................................................... 181 Frame Sync, AC-Link Start-Of-Frame....................... 124 Frame Sync, Multichannel Mode ..............................
dsPIC30F3014/4013 NOTES: DS70138G-page 224 2010 Microchip Technology Inc.
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