Datasheet

© 2010 Microchip Technology Inc. DS70141F-page 89
dsPIC30F3010/3011
TABLE 13-1: OUTPUT COMPARE REGISTER MAP
(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184
—OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A
—OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC3RS
(2)
018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R
(2)
018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON
(2)
0190 —OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS
(2)
0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R
(2)
0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON
(2)
0196 —OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2: These registers are not available on dsPIC30F3010 devices.