Datasheet

dsPIC30F3010/3011

12.2.2 INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Inter-

rupt mode selected by the ICI<1:0> bits is applicable, as

well as the 4:1 and 16:1 capture prescale settings,

which are defined by control bits, ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover, the

ICSIDL bit must be asserted to a logic ‘0’.

If the input capture module is defined as ICM<2:0> = 111

in CPU Idle mode, the input capture pin will serve only as

an external interrupt pin.

12.3 Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt based upon the selected number of

capture events. The selection number is set by control

bits, ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx register.

Enabling an interrupt is accomplished via the respec-

tive Input Capture Channel Interrupt Enable (ICxIE) bit.

The capture interrupt enable bit is located in the

corresponding IEC Control register.