Datasheet

© 2010 Microchip Technology Inc. DS70141F-page 59
dsPIC30F3010/3011
7.3 Writing to the Data EEPROM
To write an EEPROM data location, the following
sequence must be followed:
1. Erase data EEPROM word.
a) Select the word, data EEPROM, erase and
set WREN bit in the NVMCON register.
b) Write the address of word to be erased into
the NVMADRU/NVMADR.
c) Enable the NVM interrupt (optional).
d) Write 0x55 to NVMKEY.
e) Write 0xAA to NVMKEY.
f) Set the WR bit. This will begin the erase cycle.
g) Either poll the NVMIF bit or wait for the
NVMIF interrupt.
h) The WR bit is cleared when the erase cycle
ends.
2. Write the data word into the data EEPROM write
latches.
3. Program 1 data word into the data EEPROM.
a) Select the word, data EEPROM, program and
set the WREN bit in the NVMCON register.
b) Enable the NVM write done interrupt
(optional).
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This will begin the program
cycle.
f) Either poll the NVMIF bit or wait for the
NVM interrupt.
g) The WR bit is cleared when the write cycle
ends.
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution. The WREN bit should be kept clear at all
times, except when updating the EEPROM. The
WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt, or poll this bit. NVMIF
must be cleared by software.
7.3.1 WRITING A WORD OF DATA
EEPROM
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 7-4.
EXAMPLE 7-4: DATA EEPROM WORD WRITE
; Point to data memory
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1
,
TBLPAG
MOV #LOW(WORD),W2 ; Get data
TBLWTL W2
,
[ W0] ; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV #0x4004,W0
MOV W0
,
NVMCON
; Operate key to allow write operation
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55,W0
MOV W0
,
NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1
,
NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete