Datasheet

dsPIC30F3010/3011
DS70141F-page 222 © 2010 Microchip Technology Inc.
PWM Operation During CPU Idle Mode............................ 101
PWM Operation During CPU Sleep Mode ........................101
PWM Output and Polarity Control .....................................100
Output Pin Control .................................................... 100
PWM Output Override......................................................... 99
Complementary Output Mode..................................... 99
Synchronization .......................................................... 99
PWM Period........................................................................ 96
PWM Special Event Trigger.............................................. 101
Postscaler .................................................................101
PWM Time Base ................................................................. 95
Continuous Up/Down Count Modes............................ 95
Double-Update Mode.................................................. 96
Free-Running Mode .................................................... 95
Postscaler ...................................................................96
Prescaler..................................................................... 96
Single-Shot Mode ....................................................... 95
PWM Update Lockout ....................................................... 101
Q
QEA/QEB Input Characteristics ........................................ 186
QEI Module
External Clock Timing Requirements........................ 182
Index Pulse Timing Characteristics........................... 187
Index Pulse Timing Requirements ............................187
Operation During CPU Idle Mode ...............................90
Operation During CPU Sleep Mode............................89
Register Map............................................................... 91
Timer Operation During CPU Idle Mode .....................90
Timer Operation During CPU Sleep Mode.................. 89
Quadrature Decoder Timing Requirements ...................... 186
Quadrature Encoder Interface (QEI) Module ......................87
Quadrature Encoder Interface Interrupts ............................90
Quadrature Encoder Interface Logic................................... 88
R
Reader Response ............................................................. 220
Reset......................................................................... 135, 141
Reset Sequence..................................................................45
Reset Sources ............................................................ 45
Reset Timing Characteristics ............................................ 178
Reset Timing Requirements.............................................. 178
Resets
BOR, Programmable................................................. 143
POR ..........................................................................141
POR with Long Crystal Start-up Time....................... 143
POR, Operating without FSCM and PWRT ..............143
Revision History ................................................................ 211
S
Simple Capture Event Mode
Capture Buffer Operation............................................ 80
Capture Prescaler ....................................................... 80
Hall Sensor Mode ....................................................... 80
Input Capture in CPU Idle Mode .................................81
Timer2 and Timer3 Selection Mode............................ 80
Simple OCx/PWM Mode Timing Requirements ................ 184
Simple Output Compare Match Mode................................. 84
Simple PWM Mode .............................................................84
Input Pin Fault Protection............................................84
Period..........................................................................85
Single Pulse PWM Operation.............................................. 99
Software Simulator (MPLAB SIM)..................................... 161
Software Stack Pointer, Frame Pointer............................... 18
CALL Stack Frame...................................................... 33
SPI Mode
Slave Select Synchronization ................................... 105
SPI1 Register Map.................................................... 106
SPI Module ....................................................................... 103
Framed SPI Support................................................. 104
Operating Function Description ................................ 103
SDOx Disable ........................................................... 103
Timing Characteristics
Master Mode (CKE = 0).................................... 188
Master Mode (CKE = 1).................................... 189
Slave Mode (CKE = 1).............................. 190, 191
Timing Requirements
Master Mode (CKE = 0).................................... 188
Master Mode (CKE = 1).................................... 189
Slave Mode (CKE = 0)...................................... 190
Slave Mode (CKE = 1)...................................... 192
Word and Byte Communication................................ 103
SPI Operation During CPU Idle Mode .............................. 105
SPI Operation During CPU Sleep Mode........................... 105
STATUS Register ............................................................... 18
System Integration............................................................ 135
Overview................................................................... 135
Register Map ............................................................ 148
T
Temperature and Voltage Specifications
AC............................................................................. 172
DC ............................................................................ 164
Timer1 Module.................................................................... 65
16-Bit Asynchronous Counter Mode........................... 65
16-Bit Synchronous Counter Mode............................. 65
16-Bit Timer Mode ...................................................... 65
Gate Operation ........................................................... 66
Interrupt ...................................................................... 67
Operation During Sleep Mode .................................... 66
Prescaler .................................................................... 66
Real-Time Clock ......................................................... 67
RTC Interrupts.................................................... 67
RTC Oscillator Operation ................................... 67
Register Map .............................................................. 68
Timer2 and Timer3 Selection Mode.................................... 84
Timer2/3 Module................................................................. 69
32-Bit Synchronous Counter Mode............................. 69
32-Bit Timer Mode ...................................................... 69
ADC Event Trigger...................................................... 72
Gate Operation ........................................................... 72
Interrupt ...................................................................... 72
Operation During Sleep Mode .................................... 72
Register Map .............................................................. 73
Timer Prescaler .......................................................... 72
Timer4/5 Module................................................................. 75
Register Map .............................................................. 78
TimerQ (QEI Module) External Clock
Timing Characteristics .............................................. 182
Timing Characteristics
SPI Module
Slave Mode (CKE = 0)...................................... 190
Timing Diagrams
A/D Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001) 200
ADC Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000).......................... 199
Band Gap Start-up Time........................................... 179
Center Aligned PWM .................................................. 97
CLKOUT and I/O ...................................................... 177