Datasheet
© 2010 Microchip Technology Inc. DS70141F-page 147
dsPIC30F3010/3011
FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 1
FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
TPWRT
TOST