Datasheet

dsPIC30F3010/3011
DS70141F-page 130 © 2010 Microchip Technology Inc.
19.4 Programming the Start of
Conversion Trigger
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. The SAMC bits must always be at least one
clock cycle.
Other trigger sources can come from timer modules,
motor control PWM module or external interrupts.
19.5 Aborting a Conversion
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
AD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multi-channel group conversion sequence.
19.6 Selecting the A/D Conversion
Clock
The A/D conversion requires 12 TAD. The source of the
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
AD.
EQUATION 19-1: A/D CONVERSION CLOCK
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
AD) must be selected to ensure a minimum TAD time
of 83.33 nsec (for VDD = 5V). Refer to Section 23.0
“Electrical Characteristics” for minimum T
AD under
other operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1: A/D CONVERSION CLOCK
CALCULATION
Note: To operate the A/D at the maximum
specified conversion speed, the auto-
convert trigger option should be selected
(SSRC = 111) and the auto-sample time
bits should be set to 1 T
AD
(SAMC = 00001). This configuration will
give a total conversion period
(sample + convert) of 13 T
AD.
The use of any other conversion trigger
will result in additional T
AD cycles to
synchronize the external event to the A/D.
TAD = TCY • (0.5 • (ADCS<5:0> + 1))
ADCS<5:0> = 2 – 1
T
AD
TCY
TAD = 154 nsec
ADCS<5:0> = 2 – 1
T
AD
TCY
TCY = 33 nsec (30 MIPS)
= 2 • – 1
154 nsec
33 nsec
= 8.33
Therefore,
Set ADCS<5:0> = 9
Actual TAD = (ADCS<5:0> + 1)
T
CY
2
= (9 + 1)
33 nsec
2
= 165 nsec