Datasheet

© 2010 Microchip Technology Inc. DS70141F-page 13
dsPIC30F3010/3011
FIGURE 1-2: dsPIC30F3010 BLOCK DIAGRAM
Instruction
Decode and
Control
OSC1/CLKI
MCLR
V DD , V SS
AN4/QEA/IC7/CN6/RB4
UARTSPI
Motor Control
PWM
Timing
Generation
AN5/QEB/IC8/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
Address Latch
Program Memory
(24 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I
2
C™
QEI
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
FLTA
/INT0/SCK1/OCFA/RE8
Input
Capture
Module
Output
Compare
Module
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PORTB
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
PORTF
PORTD
16
16
16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU
EMUD3/AN0/V REF +/CN2/RB0
EMUC3/AN1/V REF -/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
OSC2/CLKO/RC15
AV DD , AV SS
16
16
16
16
16
PORTC
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(4 Kbytes)
RAM
X Data
(4 Kbytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
16
Data EEPROM
(1 Kbyte)
16
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer