Datasheet

dsPIC30F3010/3011
DS70141F-page 108 © 2010 Microchip Technology Inc.
16.2 Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1
pin to
perform the Frame Synchronization (FSYNC) pulse
function. The control bit, SPIFSD, determines whether
the SS1
pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
FIGURE 16-1: SPI BLOCK DIAGRAM
FIGURE 16-2: SPI MASTER/SLAVE CONNECTION
Read Write
Internal
Data Bus
SDI1
SDO1
SS1
SCK1
SPI1SR
SPI1BUF
bit 0
Shift
clock
Edge
Select
F
CY
Primary
1, 4, 16, 64
Enable Master Clock
Prescaler
Secondary
Prescaler
1:1 – 1:8
SSx & FSYNC
Control
Clock
Control
Transmit
SPI1BUF
Receive
Serial Input Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIySR)
LSb
MSb
SDIy
SDOy
PROCESSOR 2
SCKy
SPI Slave
Serial Clock
Note: x = 1 or 2, y = 1 or 2.