Datasheet

© 2010 Microchip Technology Inc. DS70141F-page 223
dsPIC30F3010/3011
Dead Time .................................................................. 99
Edge-Aligned PWM..................................................... 97
External Clock........................................................... 172
I
2
C Bus Data
Master Mode..................................................... 193
Slave Mode....................................................... 195
I
2
C Bus Start/Stop Bits
Master Mode..................................................... 193
Slave Mode....................................................... 195
Input Capture (CAPx)................................................ 183
Motor Control PWM Module...................................... 185
Motor Control PWM Module Fault............................. 185
OCx/PWM Module .................................................... 184
Oscillator Start-up Timer........................................... 178
Output Compare Module........................................... 183
PWM Output ............................................................... 85
QEA/QEB Inputs....................................................... 186
QEI Module Index Pulse ........................................... 187
Reset......................................................................... 178
SPI Module
Master Mode (CKE = 0).................................... 188
Master Mode (CKE = 1).................................... 189
Slave Mode (CKE = 1)...................................... 191
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1...................... 142
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2...................... 142
Time-out Sequence on Power-up
(MCLR
Tied to VDD).......................................... 142
Timer1, 2, 3, 4, 5 External Clock............................... 180
TimerQ (QEI Module) External Clock ....................... 182
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 175
Timing Diagrams.See Timing Characteristics.
Timing Requirements
A/D Conversion
10-Bit High-speed ............................................. 201
Band Gap Start-up Time........................................... 179
Brown-out Reset ....................................................... 178
CLKOUT and I/O....................................................... 177
External Clock........................................................... 173
I
2
C Bus Data (Master Mode)..................................... 194
I
2
C Bus Data (Slave Mode)....................................... 195
Input Capture ............................................................ 183
Motor Control PWM Module...................................... 185
Oscillator Start-up Timer........................................... 178
Output Compare Module........................................... 183
Power-up Timer ........................................................ 178
QEI Module
External Clock................................................... 182
Index Pulse ....................................................... 187
Quadrature Decoder ................................................. 186
Reset......................................................................... 178
Simple OCx/PWM Mode........................................... 184
SPI Module
Master Mode (CKE = 0).................................... 188
Master Mode (CKE = 1).................................... 189
Slave Mode (CKE = 0)...................................... 190
Slave Mode (CKE = 1)...................................... 192
Timer1 External Clock............................................... 180
Timer3 and Timer5 External Clock ........................... 181
Watchdog Timer........................................................ 178
Timing Specifications
PLL Clock.................................................................. 174
Trap Vectors ....................................................................... 46
U
UART
Address Detect Mode............................................... 119
Auto Baud Support ................................................... 120
Baud Rate Generator ............................................... 119
Enabling and Setting Up UART ................................ 117
Alternate I/O ..................................................... 117
Disabling........................................................... 117
Enabling ........................................................... 117
Setting Up Data, Parity and Stop Bit Selections117
Loopback Mode........................................................ 119
Module Overview...................................................... 115
Operation During CPU Sleep and Idle Modes.......... 120
Receiving Data ......................................................... 118
In 8-Bit or 9-Bit Data Mode............................... 118
Interrupt ............................................................ 118
Receive Buffer (UxRXB)................................... 118
Reception Error Handling ......................................... 118
Framing Error (FERR) ...................................... 119
Idle Status ........................................................ 119
Parity Error (PERR).......................................... 119
Receive Break .................................................. 119
Receive Buffer Overrun Error (OERR Bit)........ 118
Transmitting Data ..................................................... 117
In 8-Bit Data Mode............................................ 117
In 9-Bit Data Mode............................................ 117
Interrupt ............................................................ 118
Transmit Buffer (UxTXB) .................................. 117
UART1 Register Map ............................................... 121
UART2 Register Map ............................................... 121
Unit ID Locations .............................................................. 135
Universal Asynchronous Receiver
Transmitter Module (UART) ..................................... 115
W
Wake-up from Sleep......................................................... 135
Wake-up from Sleep and Idle ............................................. 47
Watchdog Timer
Timing Characteristics.............................................. 178
Timing Requirements ............................................... 178
Watchdog Timer (WDT)............................................ 135, 145
Enabling and Disabling............................................. 145
Operation.................................................................. 145
WWW Address ................................................................. 219
WWW, On-Line Support ....................................................... 7