Datasheet

© 2010 Microchip Technology Inc. DS70141F-page 101
dsPIC30F3010/3011
15.3 Edge-Aligned PWM
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate Duty Cycle
register, as shown in Figure 15-2. The PWM output is
driven active at the beginning of the period (PTMR = 0)
and is driven inactive when the value in the Duty Cycle
register matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2: EDGE-ALIGNED PWM
15.4 Center-Aligned PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in a
Continuous Up/Down Count mode, as shown in
Figure 15-3.
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3: CENTER-ALIGNED PWM
15.5 PWM Duty Cycle Comparison
Units
There are three 16-bit Special Function Registers
(PDC1, PDC2 and PDC3) used to specify duty cycle
values for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16 bits wide. The
LSb of a Duty Cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1 DUTY CYCLE REGISTER BUFFERS
The three PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle, there is a Duty Cycle reg-
ister that is accessible by the user and a second Duty
Cycle register that holds the actual compare value
used in the present PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER
register occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Continuous Up/
Down Count mode, new duty cycle values are updated
when the value of the PTMR register is zero and the
PWM time base begins to count upwards. The contents
of the duty cycle buffers are automatically loaded into
the Duty Cycle registers when the PWM time base is
disabled (PTEN = 0).
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched
0
PTPER
PTMR
Value
Period
Period/2
Duty
Cycle