Datasheet

dsPIC30F1010/202X

8.4 Timer Interrupt

The 16-bit timer has the ability to generate an interrupt

on period match. When the timer count matches the

period register, the T1IF bit is asserted and an interrupt

will be generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag T1IF is

located in the IFS0 control register in the Interrupt

Controller.

When the Gated Time Accumulation mode is enabled,

an interrupt will also be generated on the falling edge of

the gate signal (at the end of the accumulation cycle).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.