Datasheet

dsPIC30F1010/202X
DS70178C-page 48 Preliminary © 2006 Microchip Technology Inc.
5.1 Interrupt Priority
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble, within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same user-
assigned priority become pending at the same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. The INT0 (external interrupt
0) may be assigned to priority level 1, thus giving it a
very low effective priority.
TABLE 5-1: dsPIC30F1010/202X
INTERRUPT VECTOR TABLE
Note: The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number
Vector
Number
Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC1 – Output Compare 1
3 11 T1 – Timer 1
4 12 Reserved
5 13 OC2 – Output Compare 2
6 14 T2 – Timer 2
7 15 T3 – Timer 3
8 16 SPI1
9 17 U1RX – UART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Write Complete
13 21 SI2C – I
2
C™ Slave Event
14 22 MI2C – I
2
C Master Event
15 23 Reserved
16 24 INT1 – External Interrupt 1
17 25 INT2 – External Interrupt 2
18 26 PWM Special Event Trigger
19 27 PWM Gen#1
20 28 PWM Gen#2
21 29 PWM Gen#3
22 30 PWM Gen#4
23 31 Reserved
24 32 Reserved
25 33 Reserved
26 34 Reserved
27 35 CN – Input Change Notification
28 36 Reserved
29 37 Analog Comparator 1
30 38 Analog Comparator 2
31 39 Analog Comparator 3
32 40 Analog Comparator 4
33 41 Reserved
34 42 Reserved
35 43 Reserved
36 44 Reserved
37 45 ADC Pair 0 Conversion Done
38 46 ADC Pair 1 Conversion Done
39 47 ADC Pair 2 Conversion Done
40 48 ADC Pair 3 Conversion Done
41 49 ADC Pair 4 Conversion Done
42 50 ADC Pair 5 Conversion Done
43 51 Reserved
44 52 Reserved
45-53 53-61 Reserved
Lowest Natural Order Priority