Datasheet

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 213
dsPIC30F1010/202X
Table 18-3 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 18-3: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Table 18-4 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 18-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR
Power-on Reset 0x000000 00000001
MCLR
Reset during normal
operation
0x000000 00100000
Software Reset during
normal operation
0x000000 00010000
MCLR Reset during Sleep 0x000000 00100010
MCLR
Reset during Idle 0x000000 00100100
WDT Time-out Reset 0x000000 00001000
WDT Wake-up PC + 2 00001010
Interrupt Wake-up from
Sleep
PC + 2
(1)
00000010
Clock Failure Trap 0x000004 00000000
Trap Reset 0x000000 10000000
Illegal Operation Trap 0x000000 01000000
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR
Power-on Reset 0x000000 0000000 1
MCLR
Reset during normal
operation
0x000000 uu10000 u
Software Reset during
normal operation
0x000000 uu01000 u
MCLR
Reset during Sleep 0x000000 uu1u001 u
MCLR Reset during Idle 0x000000 uu1u010 u
WDT Time-out Reset 0x000000 uu00100 u
WDT Wake-up PC + 2 uuuu1u1 u
Interrupt Wake-up from
Sleep
PC + 2
(1)
uuuuuu1 u
Clock Failure Trap 0x000004 uuuuuuu u
Trap Reset 0x000000 1uuuuuu u
Illegal Operation Reset 0x000000 u1uuuuu u
Legend: u = unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.