Datasheet

© 2006 Microchip Technology Inc. Preliminary DS70178C-page 199
dsPIC30F1010/202X
REGISTER 18-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R-y
HS,HC
R-y
HS,HC
R-y
HS,HC
U-0 R/W-y R/W-y R/W-y
—COSC<2:0>—NOSC<2:0>
bit 15 bit 8
R/W-0 U-0 R-0
HS,HC
R/W-0 R/C-0
HS,HC
R/W-0 U-0 R/W-0
HC
CLKLOCK
— LOCK PRCDEN CF TSEQEN — OSWEN
bit 7 bit 0
Legend: x = Bit is unknown
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR
HC = Cleared by hardware
‘1’ = Bit is set
HS = Set by hardware
‘0’ = Bit is cleared
-y = Value set from Configuration bits on POR
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only)
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator (FRC) with PLL Module
010 = Primary Oscillator (HS, EC)
011 = Primary Oscillator (HS, EC) with PLL Module
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
This bit is Reset upon:
Set to FRC value (‘000’) on POR
Loaded with NOSC<2:0> at the completion of a successful clock switch
Set to FRC value (‘000’) when FSCM detects a failure and switches clock to FRC
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator (FRC) with PLL Module
010 = Primary Oscillator (HS, EC)
011 = Primary Oscillator (HS, EC) with PLL Module
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
bit 7 CLKLOCK: Clock Lock Enabled bit
1 = If (FCKSM1 = 1), then clock and PLL configurations are locked
If (FCKSM1 = 0), then clock and PLL configurations may be modified
0 = Clock and PLL selection are not locked, configurations may be modified
Note: Once set, this bit can only be cleared via a Reset.
bit 6 Unimplemented: Read as ‘0’