Datasheet

dsPIC30F1010/202X

FIGURE 16-4: DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 1

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

TAD

adc_clk

sample_even

convert_en

capture_first_data

10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 1 2 3

sample_odd

(1)

connect_second

connectx_en

state counter

capture_second_data

connect_common

sample_odd

(2)

Dependent on S&H availability

Note 1: For all analog input pairs that do not have dedicated sample and hold circuits, the common sample and hold circuit

samples the input at the start of the first and second conversions. Therefore, the samples are sequential, not

simultaneous.

2: For all analog input pairs that have dedicated sample and hold circuits, the common sample and hold circuit samples

the input at the start of the first conversion so that both samples (odd and even) are near simultaneous.