Datasheet

dsPIC30F1010/202X
DS70178C-page 172 Preliminary © 2006 Microchip Technology Inc.
bit 2-0 ADCS<2:0>: A/D Conversion Clock Divider Select bits
If PLL is enabled (assume 15 MHz external clock as clock source):
111 = F
ADC/18 = 13.3 MHz @ 30 MIPS
110 = F
ADC/16 = 15.0 MHz @ 30 MIPS
101 = F
ADC/14 = 17.1 MHz @ 30 MIPS
100 = F
ADC/12 = 20.0 MHz @ 30 MIPS
011 = F
ADC/10 = 24.0 MHz @ 30 MIPS
010 = F
ADC/8 = 30.0 MHz @ 30 MIPS
001 = F
ADC/6 = Reserved, defaults to 30 MHz @ 30 MIPS
000 = F
ADC/4 = Reserved, defaults to 30 MHz @ 30 MIPS
If PLL is disabled (assume 15 MHz external clock as clock source):
111 = F
ADC/18 = 0.83 MHz @ 7.5 MIPS
110 = F
ADC/16 = 0.93 MHz @ 7.5 MIPS
101 = F
ADC/14 = 1.07 MHz @ 7.5 MIPS
100 = F
ADC/12 = 1.25 MHz @ 7.5 MIPS
011 = F
ADC/10 = 1.5 MHz @ 7.5 MIPS
010 = F
ADC/8 = 1.87 MHz @ 7.5 MIPS
001 = F
ADC/6 = 2.5 MHz @ 7.5 MIPS
000 = F
ADC/4 = 3.75 MHz @ 7.5 MIPS
Note: See Figure 18-2 for ADC clock derivation.
REGISTER 16-1: A/D CONTROL REGISTER (ADCON) (CONTINUED)