Datasheet
dsPIC30F1010/202X
DS70178C-page 162 Preliminary © 2006 Microchip Technology Inc.
15.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud
Rate Generator. The U1BRG register controls the
period of a free-running 16-bit timer. Equation 15-1
shows the formula for computation of the baud rate
with BRGH = 0.
EQUATION 15-1: UART BAUD RATE WITH
BRGH = 0
(1,2,3)
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
•F
CY = 7.5 MHz
• Desired Baud Rate = 9600
The maximum baud rate (BRGH = 0) possible is
F
CY/16 (for U1BRG = 0), and the minimum baud rate
possible is F
CY/(16 * 65536).
Equation 15-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 15-2: UART BAUD RATE WITH
BRGH = 1
(1,2,3)
The maximum baud rate (BRGH = 1) possible is FCY/4
(for U1BRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Writing a new value to the U1BRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
EXAMPLE 15-1: BAUD RATE ERROR CALCULATION (BRGH = 0)
(1)
Note 1: FCY denotes the instruction cycle clock
frequency (F
OSC/2).
2: Assuming external oscillator with fre-
quency of 15 MHz and PLL disabled,
F
CY is 7.5 MHz.
3: Assuming external oscillator with fre-
quency of 15 MHz and PLL enabled,
F
CY is 30 MHz.
Baud Rate =
FCY
16 • (U1BRG + 1)
FCY
16 • Baud Rate
U1BRG =
– 1
Baud Rate =
FCY
4 • (U1BRG + 1)
FCY
4 • Baud Rate
U1BRG =
– 1
Note 1: FCY denotes the instruction cycle clock
frequency.
2: Assuming external oscillator with fre-
quency of 15 MHz and PLL disabled,
F
CY is 7.5 MHz.
3: Assuming external oscillator with fre-
quency of 15 MHz and PLL enabled,
F
CY is 30 MHz.
Desired Baud Rate = Fcy/(16 (U1BRG + 1))
Solving for U1BRG value:
U1BRG = ((F
CY/Desired Baud Rate)/16) – 1
U1BRG = ((7500000/9600)/16) – 1
U1BRG = 48
Calculated Baud Rate = 7500000/(16 (48 + 1))
= 9566
Error = (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9566 – 9600)/9600
=-0.35%
Note 1: Based on TCY = 2/FOSC, PLL are disabled.