Datasheet

dsPIC30F2011/2012/3012/3013

8.6 Fast Context Saving

A context saving option is available using shadow

registers. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.S and POP.S

instructions only.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority ISR should not include the same instruc-

tions. Users must save the key registers in software

during a lower priority interrupt if the higher priority ISR

uses fast context saving.

8.7 External Interrupt Requests

The interrupt controller supports three external

interrupt request signals, INT0-INT2. These inputs are

edge sensitive; they require a low-to-high or a

high-to-low transition to generate an interrupt request.

The INTCON2 register has three bits, INT0EP-INT2EP,

that select the polarity of the edge detection circuitry.

8.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor wakes up from Sleep or Idle

and begins execution of the ISR needed to process the

interrupt request.