Datasheet

dsPIC30F2011/2012/3012/3013
DS70139G-page 204 © 2010 Microchip Technology Inc.
Trap Lockout ............................................................... 67
Uninitialized W Register Trap ..................................... 67
Watchdog Time-out..................................................... 67
Reset Timing Characteristics ............................................ 165
Reset Timing Requirements.............................................. 165
Run-Time Self-Programming (RTSP) .................................49
S
Simple Capture Event Mode ............................................... 83
Buffer Operation..........................................................84
Hall Sensor Mode ....................................................... 84
Prescaler.....................................................................83
Timer2 and Timer3 Selection Mode............................ 84
Simple OC/PWM Mode Timing Requirements.................. 171
Simple Output Compare Match Mode................................. 88
Simple PWM Mode .............................................................88
Input Pin Fault Protection............................................88
Period..........................................................................89
Software Simulator (MPLAB SIM)..................................... 147
Software Stack Pointer, Frame Pointer............................... 20
CALL Stack Frame...................................................... 39
SPI Module..........................................................................93
Framed SPI Support ................................................... 94
Operating Function Description .................................. 93
Operation During CPU Idle Mode ...............................95
Operation During CPU Sleep Mode............................95
SDOx Disable ............................................................. 94
Slave Select Synchronization ..................................... 95
SPI1 Register Map...................................................... 96
Timing Characteristics
Master Mode (CKE = 0) ....................................172
Master Mode (CKE = 1) ....................................173
Slave Mode (CKE = 1) .............................. 174, 175
Timing Requirements
Master Mode (CKE = 0) ....................................172
Master Mode (CKE = 1) ....................................173
Slave Mode (CKE = 0) ...................................... 174
Slave Mode (CKE = 1) ...................................... 176
Word and Byte Communication ..................................94
Status Bits, Their Significance and the Initialization Condition
for
RCON Register, Case 1............................................ 132
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 2 ...................................... 132
Status Register.................................................................... 20
Symbols Used in Opcode Descriptions.............................138
System Integration
Register Map............................................................. 136
T
Table Instruction Operation Summary ................................ 49
Temperature and Voltage Specifications
AC ............................................................................. 160
DC............................................................................. 150
Timer 2/3 Module ................................................................ 77
Timer1 Module .................................................................... 73
16-bit Asynchronous Counter Mode ...........................73
16-bit Synchronous Counter Mode ............................. 73
16-bit Timer Mode....................................................... 73
Gate Operation ........................................................... 74
Interrupt.......................................................................74
Operation During Sleep Mode .................................... 74
Prescaler.....................................................................74
Real-Time Clock ......................................................... 74
Interrupts............................................................. 74
Oscillator Operation ............................................ 74
Register Map .............................................................. 75
Timer2 and Timer3 Selection Mode.................................... 88
Timer2/3 Module
16-bit Timer Mode....................................................... 77
32-bit Synchronous Counter Mode............................. 77
32-bit Timer Mode....................................................... 77
ADC Event Trigger...................................................... 80
Gate Operation ........................................................... 80
Interrupt ...................................................................... 80
Operation During Sleep Mode .................................... 80
Register Map .............................................................. 81
Timer Prescaler .......................................................... 80
Timing Characteristics
A/D Conversion
Low-speed (ASAM = 0, SSRC = 000) .............. 184
Bandgap Start-up Time............................................. 166
CAN Module I/O........................................................ 181
CLKOUT and I/O ...................................................... 164
External Clock........................................................... 160
I
2
C Bus Data
Master Mode..................................................... 177
Slave Mode....................................................... 179
I
2
C Bus Start/Stop Bits
Master Mode..................................................... 177
Slave Mode....................................................... 179
Input Capture (CAPX)............................................... 169
OC/PWM Module...................................................... 171
Oscillator Start-up Timer........................................... 165
Output Compare Module .......................................... 170
Power-up Timer ........................................................ 165
Reset ........................................................................ 165
SPI Module
Master Mode (CKE = 0).................................... 172
Master Mode (CKE = 1).................................... 173
Slave Mode (CKE = 0)...................................... 174
Slave Mode (CKE = 1)...................................... 175
Type A, B and C Timer External Clock..................... 167
Watchdog Timer ....................................................... 165
Timing Diagrams
PWM Output Timing ................................................... 89
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1 ..................... 130
Time-out Sequence on Power-up
(MCLR
Not Tied to V
DD), Case 2.................................. 130
Time-out Sequence on Power-up
(MCLR
Tied to V
DD)...................................................... 130
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 163
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-speed........................................................ 185
Bandgap Start-up Time............................................. 166
Brown-out Reset....................................................... 165
CAN Module I/O........................................................ 181
CLKOUT and I/O ...................................................... 164
External Clock........................................................... 161
I
2
C Bus Data (Master Mode) .................................... 178
I
2
C Bus Data (Slave Mode) ...................................... 179
Input Capture............................................................ 169
Oscillator Start-up Timer........................................... 165
Output Compare Module .......................................... 170
Power-up Timer ........................................................ 165