Datasheet

© 2010 Microchip Technology Inc. DS70139G-page 203
dsPIC30F2011/2012/3012/3013
Interrupt Controller
Register Map......................................................... 71, 72
Interrupt Priority .................................................................. 66
Traps........................................................................... 67
Interrupt Sequence ............................................................. 69
Interrupt Stack Frame ................................................. 69
Interrupts............................................................................. 65
L
Load Conditions ................................................................ 160
Low Voltage Detect (LVD) ................................................ 133
Low-Voltage Detect Characteristics.................................. 157
LVDL Characteristics ........................................................ 157
M
Memory Organization.......................................................... 29
Core Register Map...................................................... 39
Microchip Internet Web Site.............................................. 205
Modulo Addressing ............................................................. 44
Applicability................................................................. 46
Incrementing Buffer Operation Example..................... 45
Start and End Address................................................ 45
W Address Register Selection .................................... 45
MPLAB ASM30 Assembler, Linker, Librarian ................... 146
MPLAB Integrated Development Environment Software .. 145
MPLAB PM3 Device Programmer .................................... 148
MPLAB REAL ICE In-Circuit Emulator System................. 147
MPLINK Object Linker/MPLIB Object Librarian ................ 146
N
NVM
Register Map............................................................... 53
O
OC/PWM Module Timing Characteristics.......................... 171
Operating Current (I
DD)..................................................... 152
Operating Frequency vs Voltage
dsPIC30FXXXX-20 (Extended)................................. 150
Oscillator
Configurations........................................................... 126
Fail-Safe Clock Monitor .................................... 128
Fast RC (FRC).................................................. 127
Initial Clock Source Selection ........................... 126
Low-Power RC (LPRC)..................................... 127
LP Oscillator Control......................................... 127
Phase Locked Loop (PLL) ................................ 127
Start-up Timer (OST) ........................................ 126
Operating Modes (Table).......................................... 124
System Overview...................................................... 123
Oscillator Selection ........................................................... 123
Oscillator Start-up Timer
Timing Characteristics .............................................. 165
Timing Requirements................................................ 165
Output Compare Interrupts ................................................. 90
Output Compare Module..................................................... 87
Register Map............................................................... 91
Timing Characteristics .............................................. 170
Timing Requirements................................................ 170
Output Compare Operation During CPU Idle Mode............ 90
Output Compare Sleep Mode Operation ............................ 90
P
Packaging Information ...................................................... 187
Marking ............................................................. 187, 188
Peripheral Module Disable (PMD) Registers .................... 135
Pinout Descriptions ............................................................. 16
PLL Clock Timing Specifications ...................................... 162
POR. See Power-on Reset.
Port Write/Read Example ................................................... 60
PORTB
Register Map for dsPIC30F2011/3012 ....................... 61
Register Map for dsPIC30F2012/3013 ....................... 61
PORTC
Register Map for dsPIC30F2011/2012/3012/3013 ..... 61
PORTD
Register Map for dsPIC30F2011/3012 ....................... 61
Register Map for dsPIC30F2012/3013 ....................... 62
PORTF
Register Map for dsPIC30F2012/3013 ....................... 62
Power Saving Modes........................................................ 133
Idle............................................................................ 134
Sleep ........................................................................ 133
Sleep and Idle........................................................... 123
Power-Down Current (I
PD)................................................ 154
Power-up Timer
Timing Characteristics.............................................. 165
Timing Requirements ............................................... 165
Program Address Space..................................................... 29
Construction ............................................................... 31
Data Access from Program Memory Using
Program Space Visibility..................................... 33
Data Access From Program Memory Using
Table Instructions ............................................... 32
Data Access from, Address Generation ..................... 31
Data Space Window into Operation ........................... 34
Data Table Access (LS Word).................................... 32
Data Table Access (MS Byte) .................................... 33
Memory Maps............................................................. 30
Table Instructions
TBLRDH ............................................................. 32
TBLRDL.............................................................. 32
TBLWTH............................................................. 32
TBLWTL ............................................................. 32
Program and EEPROM Characteristics............................ 159
Program Counter ................................................................ 20
Programmable .................................................................. 123
Programmer’s Model .......................................................... 20
Diagram...................................................................... 21
Programming Operations.................................................... 51
Algorithm for Program Flash....................................... 51
Erasing a Row of Program Memory ........................... 51
Initiating the Programming Sequence ........................ 52
Loading Write Latches................................................ 52
Protection Against Accidental Writes to OSCCON........... 128
R
Reader Response............................................................. 206
Reset ........................................................................ 123, 129
BOR, Programmable ................................................ 131
Brown-out Reset (BOR)............................................ 123
Oscillator Start-up Timer (OST)................................ 123
POR
Operating without FSCM and PWRT................ 131
With Long Crystal Start-up Time ...................... 131
POR (Power-on Reset)............................................. 129
Power-on Reset (POR)............................................. 123
Power-up Timer (PWRT).......................................... 123
Reset Sequence ................................................................. 67
Reset Sources............................................................ 67
Reset Sources
Brown-out Reset (BOR).............................................. 67
Illegal Instruction Trap ................................................ 67