Datasheet
© 2010 Microchip Technology Inc. DS70139G-page 15
dsPIC30F2011/2012/3012/3013
FIGURE 1-4: dsPIC30F3013 BLOCK DIAGRAM
AN8/OC1/RB8
AN9/OC2/RB9
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
V
DD
, V
SS
AN4/CN6/RB4
Low-Voltage
Detect
UART1,
Timing
Generation
AN5/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
24
24
24
24
X Data Bus
IR
I
2
C™
AN6/OCFA/RB6
EMUD2/AN7/RB7
PCU
12-bit ADC
Timers
U2TX/CN18/RF5
SCK1/INT0/RF6
Input
Capture
Module
Output
Compare
Module
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUD3/AN0/V
REF
+/CN2/RB0
PORTB
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
PORTD
16
16
16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AV
DD
, AV
SS
UART2
16
16
16
16
16
PORTC
PORTF
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(1 Kbytes)
RAM
X Data
RAM
Address
Latch
Address
Latch
EMUC2/IC1/INT1/RD8
IC2/INT2/RD9
16
EMUC3/AN1/V
REF
-/CN3/RB1
SPI1
16
(1 Kbytes)
Address Latch
Program Memory
(24 Kbytes)
Data Latch
Data EEPROM
(1 Kbytes)