Datasheet
dsPIC30F2011/2012/3012/3013
DS70139G-page 130 © 2010 Microchip Technology Inc.
FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 1
FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
TPWRT
TOST