Datasheet

© 2010 Microchip Technology Inc. DS70139G-page 117
dsPIC30F2011/2012/3012/3013
The configuration procedures in the next section pro-
vide the required setup values for the conversion
speeds above 100 ksps.
16.7.1 200 KSPS CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 16-1.
• Connect external V
REF+ and VREF- pins following
the recommended circuit shown in Figure 16-2.
• Set SSRC<2.0> = 111 in the ADCON1 register to
enable the auto convert option.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3.0> control bits in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the ADC clock period to be:
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 T
AD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The TAD selection in
conjunction with the guidelines described above allows
a conversion speed of 200 ksps. See Example 16-1 for
code example.
16.8 A/D Acquisition Requirements
The analog input model of the 12-bit ADC is shown in
Figure 16-3. The total sampling time for the A/D is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
HOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
source impedance (RS), the interconnect
impedance (R
IC) and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge the capacitor CHOLD. The combined
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the ADC, the
maximum recommended source impedance, R
S,
is 2.5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
FIGURE 16-3: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
1
(14 + 1) x 200,000
= 334 ns
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I leakage
R
IC ≤ 250Ω
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 18 pF
± 500 nA
Legend: CPIN
VT
I leakage
R
IC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.
RSS ≤ 3 kΩ