Datasheet

© 2011 Microchip Technology Inc. DS70118J-page 117
dsPIC30F2010
18.7.3.3 600 ksps Configuration Items
The following configuration items are required to
achieve a 600 ksps conversion rate.
• Comply with conditions provided in Table 18-2
• Connect external V
REF+ and VREF- pins following
the recommended circuit shown in Figure 18-2
• Set SSRC<2:0> = 111 in the ADCON1 register to
enable the auto-convert option
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable sequential sampling by clearing the
SIMSAM bit in the ADCON1 register
• Enable at least two sample and hold channels by
writing the CHPS<1:0> control bits in the
ADCON2 register
• Write the SMPI<3:0> control bits in the ADCON2
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI<3:0> = 0001 since at least two sample and
hold channels should be enabled
• Configure the A/D clock period to be:
by writing to the ADCS<5:0> control bits in the
ADCON3 register
• Configure the sampling time to be 2 T
AD by
writing: SAMC<4:0> = 00010
Select at least two channels per analog input pin by
writing to the ADCHS register.
18.8 A/D Acquisition Requirements
The analog input model of the 10-bit ADC is shown in
Figure 18-3. The total sampling time for the A/D is a
function of the internal amplifier settling time, device
V
DD and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy, the
charge holding capacitor (C
HOLD) must be allowed to
fully charge to the voltage level on the analog input pin.
The source impedance (R
S), the interconnect
impedance (R
IC), and the internal sampling switch
(R
SS) impedance combine to directly affect the time
required to charge the capacitor C
HOLD. The combined
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor within
the chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the A/D converter,
the maximum recommended source impedance, R
S, is
5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
The user must allow at least 1 T
AD period of sampling
time, T
SAMP, between conversions to allow each sam-
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the A/D con-
verter. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Electrical Specifications for T
AD and sample time
requirements.
FIGURE 18-3: ADC ANALOG INPUT MODEL
1
12 x 600,000
= 138.89 ns
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I leakage
RIC ≤ 250Ω
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 4.4 pF
± 500 nA
Legend: CPIN
VT
I leakage
R
IC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
RSS ≤ 3 kΩ