Datasheet

dsPIC30F2010
DS70118J-page 104 © 2011 Microchip Technology Inc.
FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM
Read
URX8
UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
– Generate Flags
– Generate Interrupt
UxRXIF
UxRX
· S tart bit Detect
Receive Shift Register
16 Divider
Control
Signals
UxSTA
– Shift Data Characters
Read Read
Write
Write
to Buffer
8-9
(UxRSR)
PERR
FERR
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
16X Baud Clock from
Baud Rate Generator
Note: x = 1 only.