Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 28 S (6x6) 16-Bit 30 null I/O number 20

dsPIC30F2010

Data Sheet

High-Performance,

16-bit Digital Signal Controllers

Summary of content (202 pages)

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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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dsPIC30F2010 High-Performance, 16-bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 Special Digital Signal Controller Features: CMOS Technology: • • • • • Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical) • Data EEPROM memory: - 100,000 erase/write cycle (min.
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dsPIC30F2010 Pin Diagrams 28-Pin SDIP and SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC30F2010 MCLR EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 VDD EMUD2/OC2/IC2/INT2/RD1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/S
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dsPIC30F2010 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU Architecture Overview........................................................................................................................................................ 11 3.0 Memory Organization ...............................................................................
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dsPIC30F2010 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller 8 16 24 Address Latch Data EEPROM (1 Kbyte) 16 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data Latch X Data RAM (256 bytes) Address Latch 16 16 24 Program Memory (12 Kbytes) 16 Data Latch Y Data RAM (256 bytes) Address Latch PSV and Table Data Access 24 Control Block 16 16 EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/IND
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dsPIC30F2010 Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN5 I Analog Pin Name Description Analog input channels. AVDD P P Positive supply for analog module.
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dsPIC30F2010 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PGD PGC I/O I ST ST In-Circuit Serial Programming™ (ICSP™) data input/output pin. In-Circuit Serial Programming clock input pin. RB0-RB5 I/O ST PORTB is a bidirectional I/O port. Pin Name Description RC13-RC14 I/O ST PORTC is a bidirectional I/O port. RD0-RD1 I/O ST PORTD is a bidirectional I/O port. RE0-RE5, RE8 I/O ST PORTE is a bidirectional I/O port.
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dsPIC30F2010 2.0 Note: 2.1 CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 2.2 Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped.
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dsPIC30F2010 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
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dsPIC30F2010 2.3 Divide Support 2.4 The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • • • • • DIVF – 16/16 signed fractional divide DIV.sd – 32/16 signed divide DIV.ud – 32/16 unsigned divide DIV.sw – 16/16 signed divide DIV.
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dsPIC30F2010 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Saturate Adder Carry/Borrow In Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc.
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dsPIC30F2010 2.4.1 MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value, which is sign-extended to 40 bits.
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dsPIC30F2010 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
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dsPIC30F2010 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.
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dsPIC30F2010 Note: 3.1 MEMORY ORGANIZATION FIGURE 3-1: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Instruction Access TBLRD/TBLWT TBLRD/TBLWT Program Space Visibility FIGURE 3-2: <23> User User (TBLPAG<7> = 0) Configuration (TBLPAG<7> = 1) User Program Space Address <22:16> <15> <14:1> <0> 0 PC<22:1> 0 TBLPAG<7:0> Data EA <15:0> TBLPAG<7:0> Data EA <15:0> 0 PSVPAG<7:0> Data EA <14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Using Program Space Vis
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dsPIC30F2010 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of Table Instructions are provided to move byte or word-sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
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dsPIC30F2010 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
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dsPIC30F2010 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x100100 0x0000 PSVPAG(1) 0x00 8 15 EA<15> = 0 Data Space EA 16 15 EA<15> = 1 0x8000 Address 15 Concatenation 23 23 15 0 0x001200 Upper half of Data Space is mapped into Program Space 0x001FFE 0xFFFF BSET MOV MOV MOV CORCON,#2 #0x00, W0 W0, PSVPAG 0x9200, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit regis
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dsPIC30F2010 FIGURE 3-6: DATA SPACE MEMORY MAP MSB Address MSB SFR Space (See Note) 0x0001 LSB Address 16 bits LSB 0x0000 SFR Space 0x07FE 0x0800 0x07FF 0x0801 2560 bytes Near Data Space X Data RAM (X) 256 bytes 512 bytes SRAM Space 0x08FF 0x0901 0x08FE 0x0900 Y Data RAM (Y) 256 bytes 0x09FF 0x0A00 (See Note) 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF Note: DS70118J-page 24 0xFFFE Unimplemented SFR or SRAM locations read as ‘0’.
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dsPIC30F2010 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR Space SFR Space X Space FIGURE 3-7: Unused Y Space Unused X Space X Space (Y Space) Unused Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2011 Microchip Technology Inc.
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dsPIC30F2010 3.2.2 DATA SPACES 3.2.3 The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.
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dsPIC30F2010 A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate only on words. 3.2.
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SFR Name CORE REGISTER MAP Address (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State W0 0000 W0 / WREG 0000 0000 0000 0000 W1 0002 W1 0000 0000 0000 0000 W2 0004 W2 0000 0000 0000 0000 W3 0006 W3 0000 0000 0000 0000 W4 0008 W4 0000 0000 0000 0000 W5 000A W5 0000 0000 0000 0000 W6 000C W6 0000 0000 0000 0000 W7 000E W7 0000 0000 0000 0000 W8 0010 W8 0000 0000 0000 0000 W9 0012 W9
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dsPIC30F2010 4.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 4.1.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or 5-bit literal. The result location can be either a W register or an address location.
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dsPIC30F2010 4.2 Modulo Addressing Modulo addressing is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both).
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dsPIC30F2010 FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV MOV MOV MOV MOV MOV MOV MOV DO MOV AGAIN: 0x1100 #0x1100,W0 W0, XMODSRT #0x1163,W0 W0,MODEND #0x8001,W0 W0,MODCON #0x0000,W0 #0x1110,W1 AGAIN,#0x31 W0, [W1++] INC W0,W0 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;W0 holds buffer fill value ;point W1 to buffer ;fill the 50 buffer locations ;fill the next location ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Lengt
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dsPIC30F2010 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the effective address calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
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dsPIC30F2010 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0
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dsPIC30F2010 5.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 5.1 Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assigned priority levels are from 0, as the lowest priority, to level 7, as the highest priority.
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dsPIC30F2010 5.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset, which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location, immediately followed by the address target for the GOTO instruction.
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dsPIC30F2010 Address Error Trap: 5.3.2 This trap is initiated when any of the following circumstances occurs: It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 5-1 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault. 1. 2. 3. 4. A misaligned data word access is attempted.
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dsPIC30F2010 5.4 Interrupt Sequence 5.5 All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending interrupt request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the interrupt enable (IECx) register is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated.
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SFR Name Addr.
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dsPIC30F2010 6.0 FLASH PROGRAM MEMORY Note: Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices, and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F2010 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary.
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dsPIC30F2010 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
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dsPIC30F2010 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.
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dsPIC30F2010 7.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the WR and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-2.
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dsPIC30F2010 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM, erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADRU/NVMADR. c) Enable NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
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dsPIC30F2010 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: MOV MOV MOV MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV MOV DISI MOV MOV MOV MOV BSET NOP NOP 7.
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dsPIC30F2010 8.0 Note: I/O PORTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared between the peripherals and the parallel I/O ports.
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dsPIC30F2010 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channel will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input.
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dsPIC30F2010 9.0 Note: TIMER1 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 16-bit general purpose Timer1 module and associated operational modes. Figure 9-1 depicts the simplified block diagram of the 16-bit Timer1 Module.
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dsPIC30F2010 FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) PR1 Equal Comparator x 16 TSYNC 1 Reset Sync (3) TMR1 0 0 1 Q D Q CK TGATE TCS TGATE T1IF Event Flag TGATE TON SOSCO/ T1CK 1X LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high.
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dsPIC30F2010 9.4 Timer Interrupt 9.5.1 The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the period register, the T1IF bit is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The timer interrupt flag T1IF is located in the IFS0 control register in the Interrupt Controller.
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SFR Name Addr. TMR1 0100 PR1 0102 TIMER1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer 1 Register Period Register 1 T1CON Legend: — TSIDL — — 0104 TON u = uninitialized bit; — = unimplemented bit, read as ‘0’ — — — — TGATE Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F2010 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 32-bit general purpose Timer module (Timer2/3) and associated operational modes.
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dsPIC30F2010 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 PR2 0 T3IF Event Flag 1 D Q CK TGATE(T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q TON T2CK Note: TCKPS<1:0> 2 1X Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation.
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dsPIC30F2010 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) PR2 Equal Reset Comparator x 16 TMR2 Sync 0 T2IF Event Flag Q D Q CK TGATE TCS TGATE 1 TGATE TON T2CK TCKPS<1:0> 2 1X FIGURE 10-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) PR3 ADC Event Trigger Equal Reset TMR3 0 1 Q D Q CK TGATE Sync See NOTE TON TCKPS<1:0> 2 1 X 0 1 TCY Note: TGATE TCS TGATE T3IF Event Flag Comparator x 16 Prescaler 1, 8, 64, 256 0
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dsPIC30F2010 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
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dsPIC30F2010 11.0 INPUT CAPTURE MODULE Note: The key operational features of the Input Capture module are: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F2010 11.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • • • • • Capture every falling edge Capture every rising edge Capture every 4th rising edge Capture every 16th rising edge Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM<2:0> (ICxCON<2:0>). 11.1.1 CAPTURE PRESCALER There are four input capture prescaler settings, specified by bits ICM<2:0> (ICxCON<2:0>).
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dsPIC30F2010 11.2 Input Capture Operation During Sleep and Idle Modes An input capture event will generate a device wake-up or interrupt, if enabled, if the device is in CPU Idle or Sleep mode. Independent of the timer being enabled, the input capture module will wake-up from the CPU Sleep or Idle mode when a capture event occurs, if ICM<2:0> = 111 and the interrupt enable bit is asserted. The same wake-up can generate an interrupt, if the conditions for processing the interrupt have been satisfied.
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SFR Name Addr.
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dsPIC30F2010 12.0 OUTPUT COMPARE MODULE Note: The key operational features of the Output Compare module include: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F2010 12.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 12.
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dsPIC30F2010 12.4.2 12.5 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 12-1. EQUATION 12-1: PWM PERIOD PWM period = [(PRx) + 1] • 4 • TOSC • (TMRx prescale value) PWM frequency is defined as 1/[PWM period]. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set.
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OUTPUT COMPARE REGISTER MAP SFR Name Addr.
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dsPIC30F2010 13.0 Note: QUADRATURE ENCODER INTERFACE (QEI) MODULE The Quadrature Encoder Interface (QEI) is a key feature requirement for several motor control applications, such as Switched Reluctance (SR) and AC Induction Motor (ACIM). The operational features of the QEI are, but not limited to: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F2010 13.1 Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward.
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dsPIC30F2010 13.3 Position Measurement Mode There are two Measurement modes which are supported and are termed x2 and x4. These modes are selected by the QEIM<2:0> mode select bits located in SFR QEICON<10:8>. When control bits QEIM<2:0> = 100 or 101, the x2 Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter increment rate. Every rising and falling edge of the Phase A signal causes the position counter to be incremented or decremented.
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dsPIC30F2010 13.7 QEI Module Operation During CPU Idle Mode Since the QEI module can function as a quadrature encoder interface, or as a 16-bit timer, the following section describes operation of the module in both modes. 13.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI module will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR.
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© 2011 Microchip Technology Inc. TABLE 13-1: QEI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 QEICON 0122 CNTERR — DFLTCON 0124 — — POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000 MAXCNT Legend: 0128 — = unimplemented bit, read as ‘0’ Maximun Count<15:0> 1111 1111 1111 1111 Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F2010 14.0 Note: MOTOR CONTROL PWM MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This module simplifies the task of generating multiple, synchronized Pulse Width Modulated (PWM) outputs.
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dsPIC30F2010 FIGURE 14-1: PWM BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFR FLTACON FLTA Pin Control SFR OVDCON PWM Manual Control SFR PWM Generator 3 16-bit Data Bus PDC3 Buffer PDC3 Comparator PWM Generator 2 PTMR PWM3H Channel 3 Dead-Time Generator and Override Logic Channel 2 Dead-Time Generator and Override Logic PWM3L Output Driver Block PWM2H PWM2L Comparator PWM Generator 1 PTPER Channel 1 Dead-Time Generator and Override Logic PWM1H PWM1L
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dsPIC30F2010 14.1 PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a read-only status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR.
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dsPIC30F2010 14.1.4 DOUBLE UPDATE MODE 14.2 PWM Period In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. PTPER is a 15-bit register and is used to set the counting period for the PWM time base. PTPER is a doublebuffered register.
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dsPIC30F2010 14.3 Edge-Aligned PWM Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free Running or Single Shot mode. For edge-aligned PWM outputs, the output has a period specified by the value in PTPER and a duty cycle specified by the appropriate duty cycle register (see Figure 14-2). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the duty cycle register matches PTMR.
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dsPIC30F2010 14.5.1 DUTY CYCLE REGISTER BUFFERS The four PWM duty cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a duty cycle register that is accessible by the user and a second duty cycle register that holds the actual compare value used in the present PWM period. For edge-aligned PWM output, a new duty cycle value will be updated whenever a match with the PTPER register occurs and PTMR is reset.
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dsPIC30F2010 FIGURE 14-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL 14.8 Independent PWM Output An independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMOD bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously.
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dsPIC30F2010 14.11 PWM Output and Polarity Control 14.12.2 There are three device Configuration bits associated with the PWM module that provide PWM output pin control: The FLTACON special function register has eight bits that determine the state of each PWM I/O pin when it is overridden by a FLTA input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state.
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dsPIC30F2010 14.14 PWM Special Event Trigger The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The special event trigger allows the user to minimize the delay between the time when A/D conversion results are acquired, and the time when the duty cycle value is updated.
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PWM REGISTER MAP SFR Name Addr.
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dsPIC30F2010 15.0 Note: SPI MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI) module is a synchronous serial interface.
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dsPIC30F2010 15.2 Framed SPI Support pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. The module supports a basic framed SPI protocol in Master or Slave mode.
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dsPIC30F2010 15.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode, with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled, and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset.
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SPI1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 — — Bit 9 Bit 8 Bit 7 Bit 6 SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — SPI1BUF Legend: 0224 — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F2010 16.0 Note: I2C™ MODULE 16.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F2010 FIGURE 16-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70118J-page 96 Write I2CBRG FCY Read © 2011 Microchip Technology Inc.
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dsPIC30F2010 16.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 LSbs of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
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dsPIC30F2010 16.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 16.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 16.5.1 In Slave Transmit modes, clock stretching is always performed, irrespective of the STREN bit.
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dsPIC30F2010 16.8 Slope Control The I2C standard requires slope control on the SDA and SCL signals for Fast Mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control, if desired. It is necessary to disable the slew rate control for 1 MHz mode. 16.9 IPMI Support The control bit IPMIEN enables the module to support Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. 16.
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dsPIC30F2010 16.12.4 CLOCK ARBITRATION Clock arbitration occurs when the master de-asserts the SCL pin (SCL allowed to float high) during any receive, transmit or Restart/Stop condition. When the SCL pin is allowed to float high, the Baud Rate Generator is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of I2CBRG and begins counting.
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dsPIC30F2010 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 17.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F2010 FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE URX8 Write UxSTA UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 LPBACK UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Control Signals FERR Load RSR to Buffer Receive Shift Register (UxRSR) 1 PERR From UxTX 16 Divider 16X Baud Clock from Baud Rate Generator UxRXIF Note: x = 1 o
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dsPIC30F2010 17.2 17.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 only). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 17.2.2 17.3 17.3.1 1. 2. 3. Disabling the UART module resets the buffers to empty states.
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dsPIC30F2010 17.3.4 TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR). This means that the transmit buffer has at least one empty word.
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dsPIC30F2010 17.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read-only FERR bit is buffered along with the received data. It is cleared on any Reset. 17.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
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dsPIC30F2010 17.10 UART Operation During CPU Sleep and Idle Modes 17.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘1’. Similarly, if entry into Sleep mode occurs while a reception is in progress, then the reception is aborted.
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© 2011 Microchip Technology Inc. TABLE 17-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — Bit 10 ALTIO Bit 9 Bit 8 Bit 7 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — U1TXREG 0210 — — — — — U1RXREG 0212 — — — — — U1BRG Legend: 0214 u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F2010 18.0 10-BIT HIGH-SPEED ANALOGTO-DIGITAL CONVERTER (ADC) MODULE Note: The ADC module has six 16-bit registers: • • • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The ADCON1, ADCON2 and ADCON3 registers control the operation of the ADC module.
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dsPIC30F2010 18.1 A/D Result Buffer The module contains a 16-word dual port read-only buffer, called ADCBUF0 through ADCBUFF, to buffer the ADC results. The RAM is 10 bits wide, but is read into different format 16-bit words. The contents of the sixteen ADC conversion result buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 18.2 Conversion Operation After the ADC module has been configured, the sample acquisition is started by setting the SAMP bit.
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dsPIC30F2010 18.4 Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit will cause the conversion trigger. When SSRC<2:0> = 111 (Auto-Start mode), the conversion trigger is under A/D clock control.
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dsPIC30F2010 18.7 A/D Conversion Speeds The dsPIC30F 10-bit ADC specifications permit a maximum 1 Msps sampling rate. Table 18-1 summarizes the conversion speeds for the dsPIC30F 10-bit ADC and the required operating conditions. The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external VREF pins usage and there are some differences in the configuration procedure.
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dsPIC30F2010 TABLE 18-1: 10-BIT A/D CONVERSION RATE PARAMETERS dsPIC30F 10-bit A/D Converter Conversion Rates A/D Speed Up to 1 Msps(1) TAD Sampling Minimum Time Min 83.33 ns 12 TAD RS Max VDD Temperature 500Ω 4.5V to 5.5V -40°C to +85°C A/D Channels Configuration VREF- VREF+ CH1, CH2 or CH3 ANx S/H ADC CH0 S/H Up to 750 ksps(1) 95.24 ns 2 TAD 500Ω 4.5V to 5.5V -40°C to +85°C VREF- VREF+ ANx Up to 600 ksps(1) 138.89 ns 12 TAD 500Ω 3.0V to 5.
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dsPIC30F2010 18.7.1 1 Msps CONFIGURATION GUIDELINE The configuration for 1 Msps operation is dependent on whether a single input pin is to be sampled or whether multiple pins will be sampled. 18.7.1.1 Single Analog Input For conversions at 1 Msps for a single analog input, at least two sample and hold channels must be enabled. The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels.
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dsPIC30F2010 18.7.3.3 600 ksps Configuration Items The following configuration items are required to achieve a 600 ksps conversion rate.
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dsPIC30F2010 18.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. The module has three internal power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings.
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dsPIC30F2010 18.13 Configuring Analog Port Pins 18.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
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SFR Name Addr.
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dsPIC30F2010 19.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 TABLE 19-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL XT XT w/ PLL 4x XT w/ PLL 8x XT w/ PLL 16x LP HS 200 kHz-4 MHz crystal on OSC1:OSC2. 4 MHz-10 MHz crystal on OSC1:OSC2. 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled. 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled. 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1). 32 kHz crystal on SOSCO:SOSCI(2). 10 MHz-25 MHz crystal.
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dsPIC30F2010 FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<1:0> Primary Osc NOSC<1:0> Primary Oscillator Stability Detector POR Done OSWEN Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector 2 POST<1:0> Internal Fast RC Oscillator (FRC) FRC Internal Low Power RC Oscill
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dsPIC30F2010 19.2 Oscillator Configurations 19.2.1 19.2.2 INITIAL CLOCK SOURCE SELECTION In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer is included. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e., on POR, BOR and wake-up from Sleep).
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dsPIC30F2010 19.2.3 LP OSCILLATOR CONTROL Enabling the LP oscillator is controlled with two elements: • The current oscillator group bits COSC<1:0> • The LPOSCEN bit (OSCCON register) The LP oscillator is ON (even during Sleep mode) if LPOSCEN = 1. The LP oscillator is the device clock if: • COSC<1:0> = 00 (LP selected as main osc.) and • LPOSCEN = 1 Keeping the LP oscillator ON at all times allows for a fast switch to the 32 kHz system clock for lower power operation.
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dsPIC30F2010 19.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (Clock Switch and Monitor Selection bits) in the FOSC device Configuration register. If the FSCM function is enabled, the LPRC Internal oscillator will run at all times (except during Sleep mode) and will not be subject to control by the SWDTEN bit.
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dsPIC30F2010 19.3 Reset 19.3.
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dsPIC30F2010 FIGURE 19-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 19-4: VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70118J-page 128 © 2011 Microchip Technology Inc.
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dsPIC30F2010 19.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: A BOR will generate a Reset pulse which will reset the device.
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dsPIC30F2010 Table 19-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column.
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dsPIC30F2010 19.4 19.4.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 19.4.
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dsPIC30F2010 All Resets will wake-up the processor from Sleep mode. Any Reset, other than POR, will set the Sleep status bit. In a POR, the Sleep bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Sleep mode upon WDT time-out. The Sleep and WDTO status bits are both set. 19.5.2 IDLE MODE In Idle mode, the clock to the CPU is shutdown while peripherals keep running. Unlike Sleep mode, the clock source remains active.
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dsPIC30F2010 20.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F2010 Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP.
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dsPIC30F2010 TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Wb Wd Wdo Wm,Wn Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx Wxd Wy Wyd © 2011 Microchip Technology Inc. Description Base W register ∈ {W0..
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dsPIC30F2010 TABLE 20-2: Base Instr # Assembly Mnemonic 1 ADD 2 3 4 5 6 7 8 9 10 ADDC AND ASR BCLR BRA BSET BSW BTG BTSC INSTRUCTION SET OVERVIEW Assembly Syntax Description # of word s # of cycles Status Flags Affected OA,OB,SA,SB ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1
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dsPIC30F2010 TABLE 20-2: Base Instr # Assembly Mnemonic 11 BTSS 12 13 14 15 BTST BTSTS CALL CLR INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C BTST.
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dsPIC30F2010 TABLE 20-2: Base Instr # INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of word s # of cycles Status Flags Affected 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indi
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dsPIC30F2010 TABLE 20-2: Base Instr # Assembly Mnemonic 52 NEG 53 54 NOP POP INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax PUSH # of word s # of cycles Status Flags Affected NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f=f+1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Sta
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dsPIC30F2010 TABLE 20-2: Base Instr # Assembly Mnemonic 72 SUB 73 74 75 76 SUBB SUBR SUBBR SWAP INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of word s # of cycles 1 1 Status Flags Affected SUB Acc Subtract Accumulators OA,OB,OAB, SA,SB,SAB SUB f f = f - WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1
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dsPIC30F2010 21.
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dsPIC30F2010 21.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 21.
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dsPIC30F2010 21.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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dsPIC30F2010 21.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 21.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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dsPIC30F2010 22.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
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dsPIC30F2010 22.1 DC Characteristics TABLE 22-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30F2010-30I dsPIC30F2010-20E 30 — 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 20 — 3.0-3.6V -40°C to 125°C — 15 2.5-3.
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dsPIC30F2010 TABLE 22-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units 2.5 — 5.5 V Industrial temperature Extended temperature Conditions Operating Voltage(2) DC10 VDD Supply Voltage DC11 VDD Supply Voltage 3.0 — 5.5 V DC12 VDR RAM Data Retention Voltage(3) 1.
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dsPIC30F2010 TABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Operating Current (IDD)(1) DC31a 1.6 3 mA 25°C DC31b 1.6 3 mA 85°C 3.3V DC31c 1.6 3 mA 125°C 0.128 MIPS LPRC (512 kHz) DC31e 3.9 7 mA 25°C DC31f 3.5 7 mA 85°C 5V DC31g 3.
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dsPIC30F2010 TABLE 22-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Operating Current (IDD)(1) DC51a 1.5 3.0 mA 25°C DC51b 1.5 3.0 mA 85°C DC51c 1.5 3.0 mA 125°C DC51e 4.1 7 mA 25°C DC51f 3.6 7 mA 85°C DC51g 3.
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dsPIC30F2010 TABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical Max Units — μA Conditions Power Down Current (IPD)(1) DC60a 0.05 25°C DC60b 3 25 μA 85°C DC60c 20 50 μA 125°C DC60e 0.
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dsPIC30F2010 TABLE 22-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
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dsPIC30F2010 TABLE 22-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VOL DO10 Characteristic VOH Typ(1) Max Units Conditions Output Low Voltage(2) I/O ports DO16 Min — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V OSC2/CLKO — — 0.6 V IOL = 1.
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dsPIC30F2010 TABLE 22-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Characteristic BOR Voltage(2) on VDD transition high to low BORV = 11(3) Min Typ(1) Max Units — — — V Conditions Not in operating range BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V — — BORV = 00 4.58 — 4.
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dsPIC30F2010 22.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 22-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table 22-1.
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dsPIC30F2010 TABLE 22-13: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic Min Typ(1) Max Units External CLKI Frequency(2) (External clocks allowed only in EC mode) DC 4 4 4 — — — — 40 10 10 7.5 MHz MHz MHz MHz EC EC with 4x PLL EC with 8x PLL EC with 16x PLL Oscillator Frequency(2) DC 0.
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dsPIC30F2010 TABLE 22-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units Conditions OS50 FPLLI PLL Input Frequency Range(2) 4 4 4 4 4 4 — — — — — — 10 10 7.5(3) 10 10 7.
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dsPIC30F2010 TABLE 22-16: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator Mode EC XT Note 1: 2: 3: FOSC (MHz)(1) TCY (μsec)(2) MIPs(3) w/o PLL MIPs(3) w PLL x4 MIPs(3) w PLL x8 MIPs(3) w PLL x16 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 — 10 0.4 2.5 10.0 20.0 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Assumption: Oscillator Postscaler is divided by 1. Instruction Execution Cycle Time: TCY = 1/MIPs.
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dsPIC30F2010 FIGURE 22-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 22-2 for load conditions. TABLE 22-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 FIGURE 22-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR SY10 Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 22-2 for load conditions. TABLE 22-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-6: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap Stable SY40 Note: Band Gap is enabled when FBORPOR<7> is set. TABLE 22-21: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param No. SY40 Note 1: 2: Symbol TBGAP Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-7: TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: “x” refers to Timer Type A or Timer Type B. Refer to Figure 22-2 for load conditions. TABLE 22-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 TABLE 22-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Synchronous, no prescaler 0.5 TCY + 20 — — ns Synchronous, with prescaler 10 — — ns Synchronous, no prescaler 0.
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dsPIC30F2010 FIGURE 22-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 22-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 FIGURE 22-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 22-2 for load conditions. TABLE 22-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 FIGURE 22-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 22-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F2010 FIGURE 22-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 22-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 22-2 for load conditions. TABLE 22-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-14: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 22-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 FIGURE 22-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 22-31: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx BIT14 - - - - - -1 SP31 SDIx LSb SP30 MSb IN LSb IN BIT14 - - - -1 SP40 SP41 Note: Refer to Figure 22-2 for load conditions. TABLE 22-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 BIT14 - - - - - -1 MSb SDOX SP40 SDIX LSb SP30,SP31 MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure 22-2 for load conditions. TABLE 22-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb BIT14 - - - - - -1 SP51 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions. TABLE 22-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F2010 FIGURE 22-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX BIT14 - - - - - -1 LSb SP30,SP31 SDIX MSb IN BIT14 - - - -1 SP51 LSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions. DS70118J-page 174 © 2011 Microchip Technology Inc.
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dsPIC30F2010 TABLE 22-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F2010 FIGURE 22-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 22-2 for load conditions. FIGURE 22-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure 22-2 for load conditions. DS70118J-page 176 © 2011 Microchip Technology Inc.
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dsPIC30F2010 TABLE 22-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F2010 FIGURE 22-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 22-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out DS70118J-page 178 © 2011 Microchip Technology Inc.
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dsPIC30F2010 TABLE 22-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note Symbol TLO:SCL THI:SCL Characteristic Clock Low Time Clock High Time Min Max Units 100 kHz mode 4.7 — μs 400 kHz mode 1.
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dsPIC30F2010 TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply Greater of VDD - 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V — Vss - 0.3 — VSS + 0.
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dsPIC30F2010 TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. AD24 Symbol Characteristic Min. Typ Max.
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dsPIC30F2010 FIGURE 22-24: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution SET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
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dsPIC30F2010 FIGURE 22-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Execution SET ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 TCONV AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
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dsPIC30F2010 TABLE 22-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ Max.
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dsPIC30F2010 23.0 PACKAGING INFORMATION 23.1 Package Marking Information 28-Lead QFN-S Example XXXXXXXX XXXXXXXX YYWWNNN dsPIC30F2010 -30I/MM e3 060700U 28-Lead SPDIP (Skinny DIP) Example dsPIC30F2010-30I/SP 0648017 e3 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead SOIC (7.5 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC30F2010 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70118J-page 190 © 2011 Microchip Technology Inc.
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dsPIC30F2010 APPENDIX A: REVISION HISTORY Revision F (May 2006) Previous versions of this data sheet contained Advance or Preliminary Information. They were distributed with incomplete characterization data. This revision reflects these updates: • Supported I2C Slave addresses (see Table 16-1) • 10-bit A/D High-speed Conversion timing requirements (see Section 18.
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dsPIC30F2010 Revision J (February 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controller” Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”). Section 1.0 “Device Overview” Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table 1-1). Section 14.
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dsPIC30F2010 INDEX Numerics 10-bit High Speed A/D A/D Acquisition Requirements .................................. 117 Aborting a Conversion .............................................. 113 ADCHS ..................................................................... 111 ADCON1 ................................................................... 111 ADCON2 ................................................................... 111 ADCON3 ...................................................................
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dsPIC30F2010 Width ........................................................................... 26 Data EEPROM Memory ...................................................... 49 Erasing ........................................................................ 50 Erasing, Block ............................................................. 50 Erasing, Word ............................................................. 50 Protection Against Spurious Write .............................. 52 Reading...................
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dsPIC30F2010 Instruction Addressing Modes............................................. 31 File Register Instructions ............................................ 31 Fundamental Modes Supported.................................. 31 MAC Instructions......................................................... 32 MCU Instructions ........................................................ 32 Move and Accumulator Instructions............................ 32 Other Instructions.............................................
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dsPIC30F2010 Enable Bits .................................................................. 88 Fault States ................................................................. 88 Modes ......................................................................... 88 Cycle-by-Cycle.................................................... 88 Latched ............................................................... 88 PWM Operation During CPU Idle Mode.............................. 89 PWM Operation During CPU Sleep Mode ...
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dsPIC30F2010 TimerQ (QEI Module) External Clock Timing Characteristics .............................................. 165 Timing Characteristics A/D Conversion 10-Bit High-speed (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .......................... 182 10-bit High-speed (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) 183 Band Gap Start-up Time ........................................... 162 CLKO and I/O ........................................................... 160 External Clock.............
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dsPIC30F2010 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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dsPIC30F2010 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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dsPIC30F2010 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.