Datasheet

dsPIC30F2010
DS70118J-page 82 © 2011 Microchip Technology Inc.
FIGURE 14-1: PWM BLOCK DIAGRAM
PDC3
PDC3 Buffer
PWMCON1
PTPER Buffer
PWMCON2
PTPER
PTMR
Comparator
Comparator
Channel 3 Dead-Time
Generator and
PTCON
SEVTCMP
Comparator
Special Event Trigger
FLTACON
OVDCON
PWM Enable and Mode SFRs
FLTA Pin Control SFR
PWM Manual
Channel 2 Dead-Time
Generator and
Channel 1 Dead-Time
Generator and
PWM
Generator 2
PWM
Generator 1
PWM Generator 3
SEVTDIR
PTDIR
DTCON1 Dead-Time Control SFR
Special Event
Postscaler
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
16-bit Data Bus
Override Logic
Override Logic
Override Logic
Control SFR
PWM Time Base
Output
Driver
Block
Note: Details of PWM Generator 1 and 2 not shown for clarity.