Datasheet

© 2011 Microchip Technology Inc. DS70118J-page 71
dsPIC30F2010
12.0 OUTPUT COMPARE MODULE
This section describes the Output Compare module
and associated operational modes. The features pro-
vided by this module are useful in applications requiring
operational modes such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 12-1 depicts a block diagram of the Output
Compare module.
The key operational features of the Output Compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting
the appropriate bits in the 16-bit OCxCON SFR (where
x = 1 and 2).
OCxRS and OCxR in the figure represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 12-1: OUTPUT COMPARE MODE BLOCK DIAGRAM
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
OCxR
Comparator
Output
Logic
QS
R
OCM<2:0>
Output Enable
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare
channels 1and 2.
OCFA
OCTSEL
0
1
T2P2_MATCH
TMR2<15:0>
TMR3<15:0>
T3P3_MATCH
From General Purpose
(for x = 1 and 2)
0
1
Timer Module