Datasheet

© 2011 Microchip Technology Inc. DS70118J-page 197
dsPIC30F2010
TimerQ (QEI Module) External Clock
Timing Characteristics .............................................. 165
Timing Characteristics
A/D Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .......................... 182
10-bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001) 183
Band Gap Start-up Time........................................... 162
CLKO and I/O ........................................................... 160
External Clock........................................................... 156
I
2
C Bus Data
Master Mode..................................................... 176
Slave Mode....................................................... 178
I
2
C Bus Start/Stop Bits
Master Mode..................................................... 176
Slave Mode....................................................... 178
Input Capture (CAPx)................................................ 166
Motor Control PWM Module...................................... 168
Motor Control PWM Module Fault............................. 168
OC/PWM Module...................................................... 167
Oscillator Start-up Timer........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
QEI Module Index Pulse ........................................... 170
Reset......................................................................... 161
SPI Module
Master Mode (CKE = 0).................................... 171
Master Mode (CKE = 1).................................... 172
Slave Mode (CKE = 0)...................................... 173
Slave Mode (CKE = 1)...................................... 174
TimerQ (QEI Module) External Clock ....................... 165
Type A and B Timer External Clock.......................... 163
Watchdog Timer........................................................ 161
Timing Diagrams
Center-Aligned PWM .................................................. 85
Dead-Time .................................................................. 87
Edge-Aligned PWM..................................................... 85
PWM Output ............................................................... 73
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1...................... 128
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2...................... 128
Time-out Sequence on Power-up
(MCLR
Tied to VDD).......................................... 128
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 159
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
High-speed ....................................................... 184
Band Gap Start-up Time........................................... 162
Brown-out Reset ....................................................... 161
CLKO and I/O ........................................................... 160
External Clock........................................................... 157
I
2
C Bus Data (Master Mode)..................................... 177
I
2
C Bus Data (Slave Mode)....................................... 179
Input Capture ............................................................ 166
Motor Control PWM Module...................................... 168
Oscillator Start-up Timer........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
QEI Module
External Clock................................................... 165
Index Pulse ....................................................... 170
Quadrature Decoder................................................. 169
Reset ........................................................................ 161
Simple OC/PWM Mode ............................................ 167
SPI Module
Master Mode (CKE = 0).................................... 171
Master Mode (CKE = 1).................................... 172
Slave Mode (CKE = 0)...................................... 173
Slave Mode (CKE = 1)...................................... 175
Type A Timer External Clock.................................... 163
Type B Timer External Clock.................................... 164
Type C Timer External Clock.................................... 164
Watchdog Timer ....................................................... 161
Timing Specifications
PLL Clock ................................................................. 158
U
UART
Address Detect Mode............................................... 107
Auto Baud Support ................................................... 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART ................................ 105
Alternate I/O ..................................................... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and
Stop Bit Selections ................................... 105
Loopback Mode........................................................ 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data ......................................................... 106
In 8-bit or 9-bit Data Mode................................ 106
Interrupt ............................................................ 106
Receive Buffer (UxRXB)................................... 106
Reception Error Handling ......................................... 106
Framing Error (FERR) ...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR).......................................... 107
Receive Break .................................................. 107
Receive Buffer Overrun Error (OERR Bit)........ 106
Transmitting Data ..................................................... 105
In 8-bit Data Mode............................................ 105
In 9-bit Data Mode............................................ 105
Interrupt ............................................................ 106
Transmit Buffer (UxTXB) .................................. 105
UART1 Register Map ............................................... 109
Unit ID Locations .............................................................. 121
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep......................................................... 121
Wake-up from Sleep and Idle ............................................. 41
Watchdog Timer
Timing Characteristics.............................................. 161
Timing Requirements ............................................... 161
Watchdog Timer (WDT)............................................ 121, 131
Enabling and Disabling............................................. 131
Operation.................................................................. 131
WWW Address ................................................................. 199
WWW, On-Line Support ....................................................... 6