Datasheet

© 2011 Microchip Technology Inc. DS70118J-page 111
dsPIC30F2010
18.0 10-BIT HIGH-SPEED ANALOG-
TO-DIGITAL CONVERTER
(ADC) MODULE
The 10-bit high-speed Analog-to-Digital Converter
(ADC) allows conversion of an analog input signal to a
10-bit digital number. This module is based on a Suc-
cessive Approximation Register (SAR) architecture,
and provides a maximum sampling rate of 500 ksps.
The ADC module has up to 16 analog inputs which are
multiplexed into four sample and hold amplifiers. The
output of the sample and hold is the input into the con-
verter, which generates the result. The analog refer-
ence voltages are software selectable to either the
device supply voltage (AV
DD/AVSS) or the voltage level
on the (VREF+/VREF-) pin. The ADC has a unique fea-
ture of being able to operate while the device is in Sleep
mode.
The ADC module has six 16-bit registers:
• A/D Control Register1 (ADCON1)
• A/D Control Register2 (ADCON2)
• A/D Control Register3 (ADCON3)
• A/D Input Select Register (ADCHS)
• A/D Port Configuration Register (ADPCFG)
• A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers con-
trol the operation of the ADC module. The ADCHS reg-
ister selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
The block diagram of the ADC module is shown in
Figure 18-1.
FIGURE 18-1: 10-BIT HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note: The SSRC<2:0>, ASAM, SIMSAM,
SMPI<3:0>, BUFM and ALTS bits, as well
as the ADCON3 and ADCSSL registers,
must not be written to while ADON = 1.
This would lead to indeterminate results.
S/H
+
-
10-bit Result Conversion Logic
VREF+
AV
SS
AVDD
ADC
Data
16-word, 10-bit
Dual Port
Buffer
Bus Interface
AN0
AN5
AN1
AN2
AN3
AN4
AN4
AN5
AN0
AN1
AN2
AN3
CH1
CH2
CH3
CH0
AN5
AN2
AN4
AN1
AN3
AN0
AN1
VREF-
Sample/Sequence
Control
Sample
CH1,CH2,
CH3,CH0
Input MUX
Control
Input
Switches
S/H
+
-
S/H
+
-
S/H
+
-
Format