Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 99

PIC24FJ128GC010 FAMILY

bit 5 SWDTEN: Software Enable/Disable of WDT bit

(4)

1 = WDT is enabled

0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

(1)

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake from Sleep Flag bit

(1)

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

(1)

1 = Device has been in Idle mode

0 = Device has not been in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

(1)

1 = A Brown-out Reset has occurred (also set after a Power-on Reset).

0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

(1)

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the LPCFG

Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN

bit has no effect.

3: Re-enabling the regulator after it enters Standby mode will add a delay, T

VREG, when waking up from

Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from

occurring.

4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.