Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 89
PIC24FJ128GC010 FAMILY
REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DBUFWF
(1)
— CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
HIGHIF
(1,2)
LOWIF
(1,2)
DONEIF
(1)
HALFIF
(1)
OVRUNIF
(1)
— —HALFEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DBUFWF: Buffered Data Write Flag bit
(1)
1 = The content of the DMA buffer has not been written to the location specified in DMADSTn or
DMASRCn in Null Write mode
0 = The content of the DMA buffer has been written to the location specified in DMADSTn or
DMASRCn in Null Write mode
bit 14 Unimplemented: Read as ‘0’
bit 13-8 CHSEL<5:0>: DMA Channel Trigger Selection bits
See Tab le 5-1 for a complete list.
bit 7 HIGHIF: DMA High Address Limit Interrupt Flag bit
(1,2)
1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the
data RAM space
0 = The DMA channel has not invoked the high address limit interrupt
bit 6 LOWIF: DMA Low Address Limit Interrupt Flag bit
(1,2)
1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL but above the
SFR range (07FFh)
0 = The DMA channel has not invoked the low address limit interrupt
bit 5 DONEIF: DMA Complete Operation Interrupt Flag bit
(1)
If CHEN = 1:
1 = The previous DMA session has ended with completion
0 = The current DMA session has not yet completed
If CHEN =
0:
1 = The previous DMA session has ended with completion
0 = The previous DMA session has ended without completion
bit 4 HALFIF: DMA 50% Watermark Level Interrupt Flag bit
(1)
1 = DMACNTn has reached the halfway point to 0000h
0 = DMACNTn has not reached the halfway point
bit 3 OVRUNIF: DMA Channel Overrun Flag bit
(1)
1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger
0 = The overrun condition has not occurred
bit 2-1 Unimplemented: Read as ‘0’
bit 0 HALFEN: Halfway Completion Watermark bit
1 = Interrupts are invoked when DMACNTn has reached its halfway point and at completion
0 = An interrupt is invoked only at the completion of the transfer
Note 1: Setting these flags in software does not generate an interrupt.
2: Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than
DMAL) is NOT done before the actual access.