Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 69
PIC24FJ128GC010 FAMILY
TABLE 4-29: PARALLEL MASTER/SLAVE PORT REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
PMCON1 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0
0000
PMCON2 0602 BUSY —ERRORTIMEOUT— — — — RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0000
PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE — PTEN22 PTEN21 PTEN20 PTEN19 PTEN18 PTEN17 PTEN16 0000
PMCON4 0606 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000
PMCS1CF 0608 CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000
PMCS1BS 060A BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — — — — — 0200
PMCS1MD 060C ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000
PMCS2CF 060E CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000
PMCS2BS 0610 BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — — — — — 0600
PMCS2MD 0612 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000
PMDOUT1 0614 Data Out Register 1<15:8> Data Out Register 1<7:0> xxxx
PMDOUT2 0616 Data Out Register 2<15:8> Data Out Register 2<7:0> xxxx
PMDIN1 0618 Data In Register 1<15:8> Data In Register 1<7:0> xxxx
PMDIN2 061A Data In Register 2<15:8> Data In Register 2<7:0> xxxx
PMSTAT 061C IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F
Legend: — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.
TABLE 4-30: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx
RCFGCAL 0626 RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Note 1
RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0
— — — — — — — — Note 1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged
TABLE 4-31: DATA SIGNAL MODULATOR (DSM) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
MDCON 062A MDEN
—MDSIDL— — — — — — MDOE MDSLR MDOPOL — — —MDBIT0020
MDSRC 062C
— — — — — — — — SODIS — — — MS3 MS2 MS1 MS0 000x
MDCAR 062E CHODIS CHPOL CHSYNC
— CH3 CH2 CH1 CH0 CLODIS CLPOL CLSYNC — CL3 CL2 CL1 CL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.