Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 459
PIC24FJ128GC010 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (July 2012)
Original data sheet for the PIC24FJ128GC010 family of
devices.
Revision B (May 2013)
Changes descriptive title on Page 1 to “16-Bit Flash
Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta
A/D, USB On-The-Go and XLP Technology”.
Adds CoreMark
®
rating to the “High-Performance
CPU” section on Page 2.
Removes all references to JTAG device programming
throughout the document.
Corrects the default Doze mode ratio as 1:8 (previously
described as 1:1) throughout the document.
Corrects the default FRC postscaler setting to 1:2.
Corrects references in Section 10.4.6 “Deep Sleep
WDT” regarding the Configuration register for the
DSWDTOSC and DSWDPS<4:0> bits.
Changes the description of the behavior of the UERRIF
bit in the U1IR register, from “Read-Only” to “Read,
Write 1 to Clear”, in both contexts of the register.
Corrects the low end of the operating range of the volt-
age regulator, described in Section 34.2 “On-Chip
Voltage Regulator”, to 2.0V.
Updates Section 37.0 “Electrical Characteristics”:
• Adds maximum specifications to most
DC Specifications
• Adds systematic parameter numbers to existing
DC and AC Specifications that were previously
not numbered
• Moves DC Specification for USB module from
Table 37-4 to a new Table 37-15; all subsequent
tables are renumbered accordingly
• Updates most typical and maximum specifications
in the following tables:
- Table 37-12 (Band Gap Reference
(BGBUFn) Specifications)
- Table 37-19 (Operational Amplifier
Specifications)
- Table 37-28 (12-bit Pipeline A/D Module
Specifications)
- Table 37-30 (10-Bit DAC Specifications)
- Table 37-31 (16-Bit Sigma-Delta A/D
Converter
Specifications )
Other minor typographic changes and updates
throughout.