Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 403
PIC24FJ128GC010 FAMILY
bit 5 OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> =
10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
bit 4-3 WDTCLK<1:0>: WDT Clock Source Select bits
When WDTCMX = 1:
11 =LPRC
10 = Either the 31 kHz FRC source or LPRC, depending on device configuration
(2)
01 = SOSC input
00 = System clock when active, LPRC while in Sleep mode
When WDTCMX =
0:
LPRC is always the WDT clock source.
bit 2 Reserved: Configure as ‘0’
bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator mode is disabled
10 = HS Oscillator mode is selected (HS mode is used if crystal  10 MHz)
01 = XT Oscillator mode is selected (XT mode is used if crystal < 10 MHz)
00 = EC Oscillator mode is selected
REGISTER 34-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
Note 1: These bits should be treated as reserved on the 64-pin devices (PIC24FJ64GC006 and
PIC24FJ128GC006) and should always be programmed to ‘0’. The AV
REF+/CVREF+ and AVREF-/CVREF-
functions are located on RB0 and RB1 on these devices.
2: The 31 kHz FRC source is used when a Windowed WDT mode is selected and the LPRC is not being
used as the system clock. The LPRC is used when the device is in Sleep mode and in all other cases.