Datasheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 402 2012-2013 Microchip Technology Inc.
REGISTER 34-2: CW2: FLASH CONFIGURATION WORD 2
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
IESO VBTBOR WDTCMX
ALTCVREF
(
1
)
ALTADREF
(
1
)
FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-0 R/PO-1 R/PO-1
FCKSM1 FCKSM0
OSCIOFCN WDTCLK1 WDTCLK0
r
POSCMD1 POSCMD0
bit 7 bit 0
Legend: r = Reserved bit PO = Program Once bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘1’
bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14 VBTBOR: V
BAT BOR Enable bit
1 =V
BAT BOR is enabled
0 =V
BAT BOR is disabled
bit 13 WDTCMX: WDT Clock Multiplex Control bit
1 = Enables WDT clock multiplexing
0 = Disables clock multiplexing
bit 12 ALTCVREF: External CV
REF+/CVREF- Location Select bit
(1)
1 =CVREF+/CVREF- are mapped to RA9/RA10, respectively
0 =CV
REF+/CVREF- are mapped to RB0/RB1, respectively
bit 11 ALTADREF: External AV
REF+/AVREF- Location Select bit
(1)
1 =AVREF+/AVREF- are mapped to RA9/RA10, respectively
0 =AV
REF+/AVREF- are mapped to RB0/RB1, respectively
bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1: These bits should be treated as reserved on the 64-pin devices (PIC24FJ64GC006 and
PIC24FJ128GC006) and should always be programmed to ‘0’. The AV
REF+/CVREF+ and AVREF-/CVREF-
functions are located on RB0 and RB1 on these devices.
2: The 31 kHz FRC source is used when a Windowed WDT mode is selected and the LPRC is not being
used as the system clock. The LPRC is used when the device is in Sleep mode and in all other cases.