Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 376  2012-2013 Microchip Technology Inc.
REGISTER 28-1: DACxCON: DACx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
DACEN — DACSIDL DACSLP DACFM — —DACTRIG
bit 15 bit 8
U-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— DACTSEL4 DACTSEL3 DACTSEL2 DACTSEL1 DACTSEL0 DACREF1 DACREF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DACEN: DAC Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 DACSIDL: DAC Peripheral Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 DACSLP: DAC Enable Peripheral During Sleep bit
1 = DAC continues to output the most recent value of DACxDAT during Sleep mode
0 = DAC is powered down in Sleep mode; DACx output pin is controlled by the TRISx and LATx bits
bit 11 DACFM: DAC Data Format Select bit
1 = Data is left justified (data stored in DACxDAT<15:5>)
0 = Data is right justified (data stored in DACxDAT<9:0>)
bit 10-9 Unimplemented: Read as ‘0’
bit 8 DACTRIG: DAC Trigger Input Enable bit
1 = Analog output value updates when the selected (by DACTSEL<4:0>) event occurs
0 = Analog output value updates as soon as DACxDAT is written (DAC trigger is ignored)
bit 7 Unimplemented: Recommended to write as ‘1’ for code compatibility across device families
bit 6-2 DACTSEL<4:0>: DAC Trigger Source Select bits
11x = Unimplemented
101 = S/D A/D interrupt
100 = Pipeline A/D interrupt
011 = Timer1 interrupt
010 = Timer2 interrupt
001 =INT1
000 = Comparator 1 trigger
bit 1-0 DACREF<1:0>: DAC Reference Source Select bits
11 = 2.4V Internal Band Gap (2 • BGBUF0)
(1)
10 =AVDD
01 =DVREF+
00 = Reference not connected (lowest power but no DAC functionality)
Note 1: User must also enable Band Gap Buffer 0 and set BUFCON0<1:0> to ‘00’ to obtain this voltage. See
Register 25-1 for details.