Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 373
PIC24FJ128GC010 FAMILY
REGISTER 27-3: SD1CON3: S/D CONTROL REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDDIV2
(1)
SDDIV1
(1)
SDDIV0
(1)
SDOSR2 SDOSR1 SDOSR0 SDCS1 SDCS0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — SDCH2 SDCH1 SDCH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 SDDIV<2:0>: S/D Input Clock Divider/Postscaler Ratio bits
(1)
111 = Reserved
110 =64
101 =32
100 =16
011 =8
010 =4
001 =2
000 = 1 (No divider, clock selected by SDCS<1:0> provided directly to A/D)
bit 12-10 SDOSR<2:0>: S/D Oversampling Ratio (OSR) Selection bits
111 = Reserved
110 = 16 (fastest result, lowest quality)
101 =32
100 =64
011 = 128
010 = 256
001 = 512
000 = 1024 (slowest result, best quality)
bit 9-8 SDCS<1:0>: S/D A/D Module Clock Source Select bits
11 = Reserved
10 = Primary Oscillator (OSCI/CLKI)
01 = FRC (8 MHz)
(2)
00 = System clock (FOSC/2)
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 SDCH<2:0>: S/D Analog Channel Input Select bits (positive input/negative input)
1xx = Reserved
011 = Measures the reference selected by SDREFP/SDREFN (used for gain error measurements)
010 = CH1SE/SV
SS (single-ended measurement of CH1SE)
001 = CH1+/CH1- (Differential Channel 1)
000 = CH0+/CH0- (Differential Channel 0)
Note 1: To avoid overclocking or underclocking the module, set SDDIV<2:0> to obtain an A/D clock frequency
(input frequency selected by SDCS<1:0> source, divided by selected SDDIVx ratio) at or between 1 MHz
and 4 MHz.
2: 8 MHz FRC output is used directly, prior to the FRCDIV postscaler.