Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 371
PIC24FJ128GC010 FAMILY
REGISTER 27-1: SD1CON1: S/D CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0
SDON — SDSIDL SDRST r SDGAIN2 SDGAIN1 SDGAIN0
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
DITHER1 DITHER0 —VOSCAL— SDREFN SDREFP PWRLVL
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SDON: S/D Module Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SDSIDL: S/D Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 SDRST: S/D Reset bit
1 = Resets all S/D module circuitry (analog section remains in Reset as long as bit is set)
0 = Releases from Reset (Run mode)
bit 11 Reserved: Maintain as ‘0’ for proper operation
bit 10-8 SDGAIN<2:0>: S/D Gain Control bits
11x = Reserved
101 = 32
100 = 16
011 = 8
010 = 4
001 = 2
000 = 1
bit 7-6 DITHER<1:0>: Dither Mode Select bits
11 = High dither (preferred with higher Oversampling Ratio (OSR) and positive reference well below SV
DD)
10 = Medium dither (preferred for low to medium OSR and positive reference well below SV
DD)
01 = Low dither (preferred when the positive reference is at or near SV
DD)
00 = No dither
bit 5 Unimplemented: Read as ‘0’
bit 4 VOSCAL: Internal Offset Measurement Enable bit
1 = Converter is configured to sample its own internal offset error
0 = Converter is configured for normal operation
bit 3 Unimplemented: Read as ‘0’
bit 2 SDREFN: S/D Negative Reference Source Select bit
1 =SV
REF- pin
0 =SV
SS pin
bit 1 SDREFP: S/D Positive Reference Source Select bit
1 =SV
REF+ pin
0 =SV
DD pin
bit 0 PWRLVL: Analog Amplifier Bandwidth Select bit
1 = 2x bandwidth (higher power consumption compared to normal bandwidth)
0 = Normal bandwidth