Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 359

PIC24FJ128GC010 FAMILY

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ADTACT LBUSY — — — — — —

bit 15 bit 8

R-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0

ADTDLY

—ADLIF

(1)

— — — — —

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Hardware Settable bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADTACT: A/D Trigger Event Active bit

1 = A trigger event is asserted

0 = A trigger event is not asserted

bit 14 LBUSY: Trigger Control Busy bit

1 = The A/D is converting a sample entry associated with this list’s trigger

0 = The A/D is not busy with this trigger

bit 13-8 Unimplemented: Read as ‘0’

bit 7 ADTDLY: A/D Trigger Delayed Flag bit

1 = This trigger was delayed by a higher priority trigger

0 = This trigger was not delayed by a higher priority trigger

bit 6 Unimplemented: Read as ‘0’

bit 5 ADLIF: A/D Sample List Interrupt Event Flag bit

(1)

1 = An interrupt event (defined by ADLnCONH<14:13>) has occurred in Sample List n

0 = No interrupt event has occurred

bit 4-0 Unimplemented: Read as ‘0’

Note 1: ADLIF is mirrored by the corresponding SLxIF flag bit in the ADSTATL register. Setting or clearing this bit

simultaneously changes the SLxIF.