Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 354  2012-2013 Microchip Technology Inc.
REGISTER 26-5: ADSTATL: A/D STATUS LOW REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SLOV
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — r ACCIF SL3IF
(1)
SL2IF
(1)
SL1IF
(1)
SL0IF
(1)
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 SLOV: A/D Sample List Error Event bit
1 = A buffer overflow has occurred and data has been lost
0 = No buffer overflow has occurred
bit 7-6 Unimplemented: Read as ‘0’
bit 5 Reserved: Maintain as ‘0’ for normal A/D interrupt operation
bit 4 ACCIF: Accumulator Counter Interrupt Event bit
1 = Accumulator counter has counted down to zero
0 = Accumulator counter has not reached zero
bit 3 SL3IF: A/D Sample List 3 Interrupt Event bit
(1)
1 = An interrupt event (defined by ADL3CONH<14:13>) has occurred in Sample List 3
0 = An interrupt event has not occurred
bit 2 SL2IF: A/D Sample List 2 Interrupt Event bit
(1)
1 = An interrupt event (defined by ADL2CONH<14:13>) has occurred in Sample List 2
0 = An interrupt event has not occurred
bit 1 SL1IF: A/D Sample List 1 Interrupt Event bit
(1)
1 = An interrupt event (defined by ADL1CONH<14:13>) has occurred in Sample List 1
0 = An interrupt event has not occurred
bit 0 SL0IF: A/D Sample List 0 Interrupt Event bit
(1)
1 = An interrupt event (defined by ADL0CONH<14:13>) has occurred in Sample List 0
0 = An interrupt event has not occurred
Note 1: These bits mirror the ADLIF flag bits for the corresponding ADLnSTAT registers. Changes in the ADLIF bit
are simultaneously reflected in the SLxIF bits.