Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 352  2012-2013 Microchip Technology Inc.
REGISTER 26-3: ADCON3: A/D CONTROL REGISTER 3
R/W-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
ADRC
(1)
— — — SLEN3 SLEN2 SLEN1 SLEN0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS7
(2)
ADCS6
(2)
ADCS5
(2)
ADCS4
(2)
ADCS3
(2)
ADCS2
(2)
ADCS1
(2)
ADCS0
(2)
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit HC = Hardware Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: A/D Conversion Clock Source (T
SRC) bit
(1)
1 = Conversion clock derived from FRC (TSRC = TFRC)
0 = Conversion clock derived from system clock (T
SRC = TSYS)
bit 14-12 Unimplemented: Read as ‘0’
bit 11 SLEN3: A/D Sample List 3 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL3CONL<12:8> are processed
0 = Sampling for this list is disabled
bit 10 SLEN2: A/D Sample List 2 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL2CONL<12:8> are processed
0 = Sampling for this list is disabled
bit 9 SLEN1: A/D Sample List 1 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL1CONL<12:8> are processed
0 = Sampling for this list is disabled
bit 8 SLEN0: A/D Sample List 0 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL0CONL<12:8> are processed
0 = Sampling for this list is disabled
bit 7-0 ADCS<7:0>: A/D Conversion Clock Prescaler bits
(2)
TAD = TSRC·(2·ADCS<7:0>)
Except When
ADCS<7:0> = 00h:
TAD = TSRC
Otherwise:
00100001 and higher = Reserved
00100000 = 32·T
SRC
00011111 = 31·TSRC
···
00000010 = 4·T
SRC
00000001 = 2·TSRC
Note 1: This bit must be set for Sleep operation.
2: Final A/D clock frequency (1/T
AD) must be at or between 1 MHz and 10 MHz.